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Intel
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| Part No. |
A82596CA KU82596CA
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| OCR Text |
...ess generation, destination ad- dress checking, short-frame detection, and automat- ic length-field handling. data rates up to 20 mb/s are supported. the 82596ca provides a powerful host system inter- face. it manages memory structures auto... |
| Description |
High-performance 32-bit local area network coprocessor
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| File Size |
739.58K /
76 Page |
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Download Datasheet
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Fujitsu
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| Part No. |
MB85RC16
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| OCR Text |
...s (3 bits) and by the memory ad dress lower 8-bit which has saved in the memory address buffer, and saving to the memory address bu ffer and access to the memory is performed. scl 123 8 9 sda start ack the transmitter side should always re... |
| Description |
16 K (2 K x 8) Bit I2C
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| File Size |
163.04K /
20 Page |
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it Online |
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Intel Corp.
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| Part No. |
INTEL387DX
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| OCR Text |
...cessor is executing in real-ad- dress mode, protected mode, or virtual-8086 mode. all memory access is handled by the intel386 dx microprocessor; the intel387 dx mcp merely oper- ates on instructions and values passed to it by the intel386 ... |
| Description |
DX Math Coprocessor(32位数学协处理
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| File Size |
415.42K /
41 Page |
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Intel Corp.
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| Part No. |
MILITARYI387
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| OCR Text |
...6/8087 and 80286/80287 real-ad- dress mode systems. in protected mode, the i386 sx microprocessor and i387 sx math coprocessor is completely upward compatible with software for the 80286/80287 pro- tected mode system. in all modes, the i386... |
| Description |
Military i387 SX Math Coprocessor(军用I387 SX数学协处理器)
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| File Size |
528.79K /
41 Page |
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it Online |
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Motorola Semiconductor
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| Part No. |
MC68EC040
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| OCR Text |
...field. setting a bit in the ad- dress mask field causes the processor to ignore the corresponding bit in the ad- dress base field. setting some of the address mask bits to ones obtains blocks of memory larger than 16 mbytes. the low-order b... |
| Description |
Microprocessor
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| File Size |
121.03K /
18 Page |
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it Online |
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