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ICS
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| Part No. |
M2006-03
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| OCR Text |
... output clocks are differential lvpecl compatible Two downstream clocks, frequency-selectable One upstream clock, frequency-selectable RE...lvcmos/LVTTL. For US_CLK_SEL1:0 : Logic 1 1 sets divider to 12 " 10 " ""6 " 01 " ""3 " 00 " ""1 Down... |
| Description |
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
223.26K /
6 Page |
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Download Datasheet
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ICS
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| Part No. |
M2006-04
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| OCR Text |
... reference inputs support LVDS, lvpecl, as well as single-ended lvcmos, LVTTL Power-up frequency translation ratio of x32 useful for 19.44MHz input and 155.52 or 622.08MHz output Single 3.3V power supply Small 9 x 9 mm SMT (surface mount... |
| Description |
VCSO Frequency Translator
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| File Size |
300.56K /
12 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
M2006-11 M2006-21 M2006-11-622.0800
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| OCR Text |
... reference inputs support LVDS, lvpecl, as well as single-ended lvcmos, LVTTL
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input Clock VCSO Output (MHz) Freq1 (MHz) Freq (MHz) 19.44 19.53125 622.08 625.00 62... |
| Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
312.67K /
14 Page |
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it Online |
Download Datasheet |
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Integrated Circuit System
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| Part No. |
M2006-12
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| OCR Text |
...lock output pairs. Differential lvpecl. P Divider controls. lvcmos/LVTTL. (For P0_SEL, P1_SEL, see Table 5 on pg. 3. Reference clock input pair 1. Differential lvpecl or LVDS. Reference clock input selection. lvcmos/LVTTL: Logic 1 selects D... |
| Description |
VCSO BASED FEC CLOCK PLL
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| File Size |
262.41K /
8 Page |
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it Online |
Download Datasheet |
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Price and Availability
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