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Mitsubishi Electric Corporation Mitsubishi Electric, Corp.
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Part No. |
MH64D72KLG-75 MH64D72KLG-10
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OCR Text |
...ackage. - Vdd=Vddq=2.5v 0.2V
144pin 145pin
52pin 53pin
- Double data rate architecture; two data transf ers per clock cy c le - Bidirectional, data strobe (DQS) is transmitted/receiv ed with data - Dif f erential clock inputs (CLK ... |
Description |
4 /831 /838 /208-BIT (67 /108 /864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module 4831838208位(67108864 - Word72位),双数据速率同步DRAM模块
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File Size |
334.63K /
38 Page |
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