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INTEGRATED DEVICE TECHNOLOGY INC
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Part No. |
V805L15PFI9 V805L20PF V805L10PF
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OCR Text |
...ad into the synchronous fifo on every clock when wen is asserted. the output port of each fifo bank is controlled by another clock pin (rclk) and another enable pin ( ren ). the read clock can be tied to the write clock for single clock o... |
Description |
256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 256 X 18 BI-DIRECTIONAL FIFO, 12 ns, PQFP128 256 X 18 BI-DIRECTIONAL FIFO, 6.5 ns, PQFP128
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File Size |
324.56K /
26 Page |
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it Online |
Download Datasheet |
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INTERSIL[Intersil Corporation]
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Part No. |
HMP817003 HMP8170EVAL1 HMP8170CN HMP8170
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OCR Text |
...edge of CLK2 when CLK is low
every rising edge of CLK2 every rising edge of CLK2 Any rising edge of CLK2 Ignored every rising edge of CLK2 Not Allowed Any rising edge of CLK2 Ignored
NOTE: Video timing control signals include HSYNC, V... |
Description |
NTSC/PAL Video Encoder
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File Size |
398.87K /
33 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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