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				Cypress Semiconductor
Part No.	CY7C1311CV18 CY7C1311CV18-167BZC CY7C1311CV18-167BZI CY7C1315CV18 CY7C1313CV18
OCR Text	... (DLL) is enabled Operates as a qdr-I device with 1 cycle read latency in DLL off mode Available in x 8, x 9, x 18, and x 36 configurations Full data coherency, providing most current data Core VDD = 1.8 (0.1V); IO VDDQ = 1.4V to VDD Availa...
Description	18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
File Size	432.87K / 31 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT70P3337S233RM IDT70P3337S233RMI IDT70P3337S250RM IDT70P3337S250RMI
OCR Text	qdr-IITM (R) PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 Features 18Mb Density (1024K x 18) - Also available 9Mb Density (512K x 18) qdr-II x 18 Burst-of-2 Interface - Commercial: 233MHz, 250MHz Separate, Independent Read ...
Description	1024K/512K x18 SYNCHRONOUS DUAL qdr-II
File Size	873.78K / 20 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1302DV25-167BZC CY7C1302DV25-167BZI CY7C1302DV25-167BZXC CY7C1302DV25-167BZXI CY7C1302DV2506 CY7C1302DV25
OCR Text	...uipped with QDRTM architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write op...
Description	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR垄芒 Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture
File Size	383.22K / 18 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV25-167BZC CY7C1306AV25-167BZC CY7C1303AV25-133BZC CY7C1306AV25-133BZC
OCR Text	...uipped with QDRTM architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data inputs to support Write op...
Description	Memory : Sync SRAMs 18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
File Size	325.22K / 19 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1515AV18 CY7C1515AV18-167BZC CY7C1515AV18-167BZI CY7C1515AV18-167BZXC CY7C1515AV18-167BZXI CY7C1515AV18-200BZC CY7C1515AV18-200BZI CY7C1515AV18-200BZXC CY7C1515AV18-200BZXI CY7C1515AV18-250BZC CY7C1515AV18-250BZI CY7C1515AV18-250BZXC CY7C1515AV18-250BZXI CY7C1515AV18-278BZC CY7C1515AV18-278BZI CY7C1515AV18-278BZXC CY7C1515AV18-278BZXI CY7C1515AV18-300BZC CY7C1515AV18-300BZI CY7C1515AV18-300BZXC CY7C1515AV18-300BZXI CY7C1513AV18 CY7C1513AV18-167BZC CY7C1513AV18-167BZI CY7C1513AV18-167BZXC CY7C1513AV18-167BZXI CY7C1513AV18-200BZC CY7C1513AV18-200BZI CY7C1513AV18-200BZXC CY7C1513AV18-200BZXI CY7C1513AV18-250BZC CY7C1513AV18-250BZI CY7C1513AV18-250BZXC CY7C1513AV18-250BZXI CY7C1513AV18-278BZC CY7C1513AV18-278BZI CY7C1513AV18-278BZXC CY7C1513AV18-278BZXI CY7C1513AV18-300BZC CY7C1513AV18-300BZI CY7C1513AV18-300BZXC CY7C1513AV18-300BZXI
OCR Text	...us internally self-timed writes qdr-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled Operates as a qdr-I device with 1 cycle read latency in DLL off mode Available in x 8, x 9, x 18, and x 36 configurations ...
Description	72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
File Size	448.03K / 31 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1425JV18-250BZXC CY7C1425JV18-250BZXI CY7C1414JV18 CY7C1414JV18-250BZC CY7C1414JV18-250BZI CY7C1414JV18-250BZXC CY7C1414JV18-250BZXI CY7C1414JV18-267BZC CY7C1414JV18-267BZI CY7C1414JV18-267BZXC CY7C1414JV18-267BZXI CY7C1412JV18 CY7C1412JV18-250BZC CY7C1412JV18-250BZI CY7C1412JV18-250BZXC CY7C1412JV18-250BZXI CY7C1412JV18-267BZC CY7C1412JV18-267BZI CY7C1412JV18-267BZXC CY7C1412JV18-267BZXI
OCR Text	...DLL) is enabled Operates like a qdr-I device with 1 cycle read latency in DLL off mode Available in x8, x9, x18, and x36 configurations Full data coherency, providing most current data Core VDD = 1.8V (0.1V); IO VDDQ = 1.4V to VDD Available...
Description	36-Mbit QDR⑩-II SRAM 2-Word Burst Architecture
File Size	403.30K / 26 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1425V18-167BZC CY7C1425V18-200BZC CY7C1425V18-250BZC CY7C1414V18
OCR Text	qdr-IITM SRAM 2-Word Burst Architecture Features * Separate Independent Read and Write data ports -- Supports concurrent transactions * 200-MHz clock for high bandwidth * 2-Word Burst on all accesses * Double Data Rate (DDR) interfaces on...
Description	36-Mbit qdr-II(TM) SRAM 2-Word Burst Architecture 36-Mbit qdr-II?? SRAM 2-Word Burst Architecture
File Size	270.30K / 23 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1514JV18 CY7C1514JV18-250BZC CY7C1514JV18-250BZI CY7C1514JV18-250BZXC CY7C1514JV18-250BZXI CY7C1514JV18-267BZC CY7C1514JV18-267BZI CY7C1514JV18-267BZXC CY7C1514JV18-267BZXI
OCR Text	...us internally self-timed writes qdr-II operates with 1.5 cycle read latency when Delay Lock Loop (DLL) is enabled Operates like a qdr-I device with 1 cycle read latency in DLL off mode Available in x8, x9, x18, and x36 configurations Full d...
Description	72-Mbit QDR⑩-II SRAM 2-Word Burst Architecture
File Size	403.49K / 26 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1270V18 CY7C1270V18-300BZC CY7C1270V18-300BZI CY7C1270V18-300BZXC CY7C1270V18-300BZXI CY7C1270V18-333BZC CY7C1270V18-333BZXC CY7C1270V18-333BZXI CY7C1270V18-375BZC CY7C1270V18-375BZI CY7C1270V18-375BZXC CY7C1270V18-375BZXI CY7C1270V18-400BZC CY7C1270V18-400BZXC CY7C1270V18-400BZXI CY7C1266V18-333BZC CY7C1268V18-333BZC
OCR Text	...1000 Unit MHz mA Note 1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD. Cypress Semiconductor Corporation Doc...
Description	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	1,082.18K / 27 Page	View it Online	Download Datasheet

				Renesas Electronics Corporation
Part No.	R1Q2A3636ABG60RB0 R1Q3A3636ABG60RB0 R1Q4A3636ABG60RB0 R1Q5A3636ABG60RB0 R1Q6A3636ABG60RB0 R1Q2A7236ABG60RB0 R1Q3A7236ABG60RB0 R1Q4A7236ABG60RB0 R1Q5A7236ABG60RB0 R1Q6A7236ABG60RB0 R1Q2A3618ABG60RB0 R1Q3A3618ABG60RB0 R1Q4A3618ABG60RB0 R1Q5A3618ABG60RB0 R1Q6A3618ABG60RB0 R1Q2A7218ABG60RB0 R1Q3A7218ABG60RB0 R1Q4A7218ABG60RB0 R1Q5A7218ABG60RB0 R1Q6A7218ABG60RB0 R1Q2A3636ABG40RB0 R1Q2A3636ABG50RB0 R1Q3A3636ABG50RB0 R1Q4A3636ABG50RB0 R1Q5A3636ABG50RB0 R1Q6A3636ABG50RB0 R1Q2A7236ABG50RB0 R1Q3A7236ABG50RB0 R1Q4A7236ABG50RB0 R1Q5A7236ABG50RB0 R1Q6A7236ABG50RB0 R1Q2A3618ABG50RB0 R1Q3A3636ABG40RB0 R1Q4A3636ABG40RB0 R1Q5A3636ABG40RB0 R1Q6A3636ABG40RB0 R1Q2A3636ABG40RS0 R1Q3A3636ABG40RS0 R1Q4A3636ABG40RS0 R1Q5A3636ABG40RS0 R1Q6A3636ABG40RS0 R1Q2A3636ABG40RT0 R1Q3A3636ABG40RT0 R1Q4A3636ABG40RT0 R1Q5A3636ABG40RT0 R1Q6A3636ABG40RT0 R1Q2A7209ABG40RB0 R1Q3A7209ABG40RB0 R1Q4A7209ABG40RB0 R1Q5A7209ABG40RB0 R1Q6A7209ABG40RB0 R1Q2A7209ABG40RS0 R1Q3A7209ABG40RS0 R1Q4A7209ABG40RS0 R1Q5A7209ABG40RS0 R1Q6A7209ABG40RS0 R1Q2A7209ABG40RT0 R1Q3A7209ABG40RT0 R1Q4A7209ABG40RT0 R1Q5A7209ABG40RT0 R1Q6A7209ABG40RT0 R1Q2A7209ABG50RB0 R1Q3A7209ABG50RB0 R1Q4A7209ABG50RB0 R1Q5A7209ABG50RB0 R1Q6A7209ABG50RB0 R1Q2A7209ABG
OCR Text	...on JTAG boundary scan Notes: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp. Preliminary: The specifications of this device are subjec...
Description	36-Mbit QDR⑩II SRAM 2-word Burst 36-Mbit QDR垄芒II SRAM 2-word Burst
File Size	336.36K / 26 Page	View it Online	Download Datasheet

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