| |
|
 |
Cypress Semiconductor, Corp.
|
| Part No. |
CY7C1514KV18 CY7C1514KV18-300BZXC CY7C1512KV18-300BZXC CY7C1512KV18-300BZC CY7C1514KV18-300BZC CY7C1514KV18-250BZC CY7C1514KV18-250BZI CY7C1514KV18-250BZXC CY7C1514KV18-333BZC CY7C1514KV18-333BZI CY7C1514KV18-333BZXC CY7C1514KV18-333BZXI CY7C1514KV18-250BZXI CY7C1525KV18 CY7C1512KV18-350BZC
|
| OCR Text |
...es qdr ? ii operates with 1.5 cycl e read latency when doff is asserted high operates similar to qdr i device with 1 cycle read latency when doff is asserted low available in x8, x9, x18, and x36 configurations full data coherenc... |
| Description |
72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 QDR SRAM, 0.45 ns, PBGA165
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.45 ns, PBGA165
|
| File Size |
603.26K /
33 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Freescale Semiconductor
|
| Part No. |
MM912F634
|
| OCR Text |
... (pb2.0) ? low power modes with cycl ic sense & forced wake-up ? current sense module with selectable gain ? reverse battery protected voltage sense module ? two protected low side outputs to drive inductive loads ? two protected high side... |
| Description |
Integrated S12 Based Relay Driver
|
| File Size |
2,315.80K /
335 Page |
View
it Online |
Download Datasheet |
| |
|
|
聚兴科技股份有限公司
|
| Part No. |
AT25F512AN-10SH-2.7
|
| OCR Text |
...protection ? self-timed program cycl e (75 s/byt e typical) ? self-timed sector erase cycl e (1 second/se ctor typical) ? single cycle reprogramming (erase and program) for status register ? high reliability ? endurance: 10,000 write cycle... |
| Description |
|
| File Size |
440.17K /
19 Page |
View
it Online |
Download Datasheet |
| |
|
|
MAXIM - Dallas Semiconductor
|
| Part No. |
DS1216E DS1216F DS1216H
|
| OCR Text |
...irst of 64 write cycles, a read cycl e should be executed by holding a2 high. the read cycle will reset the comparison register pointer with in the smartwatch, ensuring the pattern recognition starts with the first bit of the sequence. wh... |
| Description |
SmartWatch RAM DS1216B/C/D/HSmartWatch ROM DS1216E/F
|
| File Size |
425.52K /
14 Page |
View
it Online |
Download Datasheet |
| |
|
|
Samsung Electronics
|
| Part No. |
K9F1G08R0B
|
| OCR Text |
...four cycles for addressing : 2 cycl es of column address, 2 cycles of row address, in t hat order. page read and page program need the same four address cycl es following the required command input. in block erase oper- ation, however, onl... |
| Description |
FLASH MEMORY
|
| File Size |
740.08K /
34 Page |
View
it Online |
Download Datasheet |
| |
|
|
Hanbit Electronics Co.,Ltd.
|
| Part No. |
HDD16M64B8 HDD16M64B8-13A HDD16M64B8-10A HDD16M64B8-13B
|
| OCR Text |
...nchronous design allows precise cycl e control with the use of system clock. data i/o transactions are possible on both edges of dqs . range of operating frequencies, programmable latencies and burst lengths allows the same devi... |
| Description |
DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref. SO-DIMM
|
| File Size |
162.68K /
11 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
