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Part No. |
K4T51163QE-ZPD50
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OCR Text |
... pair of bidirectional strobes (dqs and dqs ) in a source synchronous fashion. the address bus is used to convey row, column, and bank address information in a ras / cas multiplexing style. the 512mb ddr2 device operates with a single 1.8... |
Description |
32M X 16 DDR DRAM, 0.5 ns, PBGA84
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File Size |
449.51K /
25 Page |
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it Online |
Download Datasheet
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Part No. |
HYMD116645AL8 HYMD116645A8
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OCR Text |
...s of the clock ? data inputs on dqs cent ers when write (centered dq) ? data strobes synchroniz ed with output data for read and input data for write ? programmable cas latency 2 / 2.5 supported ? programmable burst length 2 / 4 / 8 with ... |
Description |
16Mx64|2.5V|K/H/L|x8|DDR SDRAM - Unbuffered DIMM 128MB
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File Size |
227.61K /
16 Page |
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it Online |
Download Datasheet
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Part No. |
HYMD1166458
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OCR Text |
...s of the clock ? data inputs on dqs centers when write (centered dq) ? data strobes synchronized with output data for read and input data for write ? programmable cas latency 2 / 2.5 supported ? programmable burst length 2 / 4 / 8 with bo... |
Description |
16Mx64|2.5V|H/L|x8|DDR SDRAM - Unbuffered DIMM 128MB
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File Size |
150.62K /
16 Page |
View
it Online |
Download Datasheet
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Price and Availability
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