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ICS
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| Part No. |
ICS8702
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| OCR Text |
...he following input types: LVDS, lvpecl, LVHSTL, SSTL, HCSL * Maximum output frequency up to 250MHz * Translates any differential input signal (lvpecl, LVHSTL, LVDS) to lvcmos levels without external bias networks * Translates any single-end... |
| Description |
Low Skew, ÷1, ÷2, Clock Generator
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| File Size |
88.01K /
15 Page |
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ICS
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| Part No. |
ICS873034
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| OCR Text |
lvpecl/ECL CLOCK GENERATOR
FEATURES
* 3 differential 2.5V, 3.3V lvpecl / ECL output * 1 differential PCLK, nPCLK input pair * PCLK, nPCLK ...lvcmos/LVTTL interface levels. Bias voltage. Pullup/ Clock input. Defaults to VCC/2 (.66) when left ... |
| Description |
Low Skew, ÷2, ÷4, ÷8, Differential-to-lvpecl Clock Generator. Industrial Temperature.
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| File Size |
256.16K /
16 Page |
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ICS
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| Part No. |
ICS8732-01
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| OCR Text |
lvpecl CLOCK GENERATOR
Features
* 10 differential 3.3V lvpecl outputs * Selectable differential CLK0, nCLK0 or lvcmos/LVTTL CLK1 inputs * CLK0, nCLK0 supports the following input types: lvpecl, LVDS, LVHSTL, SSTL, HCSL * CLK1 accepts the ... |
| Description |
Low Skew, 1-to-10, lvpecl Clock Multiplier/Zero Delay Buffer
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| File Size |
145.68K /
16 Page |
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it Online |
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ICS
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| Part No. |
ICS87322BI
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| OCR Text |
lvpecl/ECL CLOCK GENERATOR
FEATURES
* 15 differential lvpecl outputs * Selectable lvpecl differential clock inputs * CLK0, nCLK0 and CLK1,...lvcmos / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3C. LV... |
| Description |
Low Skew, ÷1, ÷2 Clock Generator. Industrial Temperature.
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| File Size |
149.45K /
15 Page |
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it Online |
Download Datasheet |
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ICS
Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
M1020 M1021 M1021-13-161.1328LF M1021-13I161.1328LF M1020-11-155.5200LF M1020-11I167.3280LF
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| OCR Text |
...ut frequency at time of order) lvpecl clock output (CML and LVDS options available) Reference clock inputs support differential LVDS, lvpecl, as well as single-ended lvcmos, LVTTL Loss of Lock (LOL) output pin Narrow Bandwidth control i... |
| Description |
Frequency Translation PLL Family with Loss of Lock indicator and Hitless Switching options
ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 9 X 9 MM, CERAMIC, LCC-36
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| File Size |
307.50K /
10 Page |
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Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
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| Part No. |
MAX9173
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| OCR Text |
...
Features
o Accepts LVDS and lvpecl Inputs o Fully Compatible with DS90LV048A o Low 1.0mA (max) Disable Supply Current o In-Path Fail-Saf...lvcmos DATA INPUTS Tx 100 Rx
LVTTL/lvcmos DATA OUTPUTS
Tx
100
Rx
Pin Configurations a... |
| Description |
Quad LVDS Line Receiver with Flow-Through Pinout and ?n-PathFail-Safe 四路LVDS线接收器，引脚按信号流向排列，带有通道失效保护
Quad LVDS Line Receiver with Flow- Through Pinout and “In-Path?Fail-Safe
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
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| File Size |
337.24K /
14 Page |
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it Online |
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MAXIM - Dallas Semiconductor
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| Part No. |
MAX9324
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| OCR Text |
lvpecl/lvcmos Output Clock and Data Driver
General Description
The MAX9324 low-skew, low-jitter, clock and data driver distributes a differential lvpecl input to four differential lvpecl outputs and one single-ended lvcmos output. All out... |
| Description |
One-to-Five lvpecl/lvcmos Output Clock and Data Driver
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| File Size |
270.02K /
12 Page |
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it Online |
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Price and Availability
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