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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
SP8647 SP8647BDG
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| OCR Text |
...odulus divider, with ECL10K and ttl/CMOS compatible outputs. It divides by 10 when either of the ECL control inputs, PE1 or PE2, is in the high state and by 11 when both are low (or open circuit). The two clock inputs are interchangeable an... |
| Description |
250MHz 10/11
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| File Size |
167.50K /
7 Page |
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it Online |
Download Datasheet
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Allegro MicroSystems, Inc.
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| Part No. |
1345CNPD
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| OCR Text |
...ecl (pecl) data outputs n cmos (ttl) link-status flag output n operation at 1.3 m m or 1.55 m m wavelengths n operating temperature range ...ecl levels, a timing recovery unit to recover the clock, and a silicon bipolar decision cir- cuit.
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| Description |
FIBER OPTIC RECEIVER 光纤接收
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| File Size |
73.78K /
12 Page |
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it Online |
Download Datasheet
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Price and Availability
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