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Altera, Corp.
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| Part No. |
EP20K400E
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| OCR Text |
...fferential signaling (lvds), lv pecl, pci-x, agp, ctt, stub- series terminated logic (s stl-3 and sstl-2), gunning transceiver logic plus (gtl+), and high-speed terminated logic (hstl class i) ? pull-up on i/o pins before and during confi... |
| Description |
Programmable Logic Device Family 可编程逻辑器件系列
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| File Size |
593.38K /
117 Page |
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it Online |
Download Datasheet
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Micrel Semiconductor, Inc.
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| Part No. |
SY89112U SY89113UMGTR
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| OCR Text |
...hen configured in single-ended pecl input mode. vbb1 can be used for ac-coupling of clk1, see figure 4d for details. maximum sink/source current is 1.5ma. due to the limited drive capability, the vbb1 pin is only intended to dr ive its r... |
| Description |
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Intermal Termination 2.5V的低抖动，低偏移1:12 LVDS扇出缓冲器的2:1输入MUX和Intermal终止
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Intermal Termination 89113 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44
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| File Size |
628.30K /
14 Page |
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it Online |
Download Datasheet |
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