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SRAM
Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
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| Part No. |
IDT70V9079L15PF IDT70V9079L15PFI IDT70V9089L15PF IDT70V9089L15PFI IDT70V9089S9PFI IDT70V9079L12PF IDT70V9079L12PFI IDT70V9079L6PF IDT70V9079L6PFI IDT70V9079L7PF IDT70V9079L7PFI IDT70V9079L9PF IDT70V9079L9PFI IDT70V9079S IDT70V9079S12PF IDT70V9079S12PFI IDT70V9079S15PF IDT70V9079S15PFI IDT70V9079S6PF IDT70V9079S6PFI IDT70V9079S7PF IDT70V9079S7PFI IDT70V9079S9PF IDT70V9079S9PFI IDT70V9089 IDT70V9089L IDT70V9089L12PF IDT70V9089L12PFI IDT70V9089L6PF IDT70V9089L6PFI IDT70V9089L7PF IDT70V9089L7PFI IDT70V9089L9PF IDT70V9089L9PFI IDT70V9089S12PF IDT70V9089S12PFI IDT70V9089S15PF IDT70V9089S15PFI IDT70V9089S6PF IDT70V9089S6PFI IDT70V9089S7PF IDT70V9089S7PFI IDT70V9089S9PF IDT70V9089S9PF8 IDT70V9079S7PF8
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| OCR Text |
.... LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
Truth Table I--Read/... |
| Description |
32K x 8 Sync, 3.3V Dual-Port RAM, PipeLined/Flow-Through
HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM 32K X 8 DUAL-PORT SRAM, 20 ns, PQFP100
HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM 64K X 8 DUAL-PORT SRAM, 20 ns, PQFP100
Small Signal Diode; Package: DO-35; No of Pins: 2; Container: Bulk
64K x 8 Sync, 3.3V Dual-Port RAM, PipeLined/Flow-Through
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| File Size |
328.73K /
19 Page |
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