| |
|
 |
Zarlink
|
| Part No. |
PDSP16330MC
|
| OCR Text |
...ndlcates that the Input data is twos' complement format (Note: input data 8000 hex is not valid in 2s' complement mode). This input refers to the format of the current Input data and may be changed on a per cycle basis if desired. The level... |
| Description |
Pythagoras Processor
|
| File Size |
81.94K /
8 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Philips
|
| Part No. |
TDA8763A TDA8763AM/3/C4 TDA8763AM/4/C4 TDA8763AM/5/C4
|
| OCR Text |
...2 23 24 25 26 27 28 clock input twos complement input (active LOW) analog supply voltage (+5 V) analog ground not connected reference voltage BOTTOM input reference voltage MIDDLE input analog input voltage reference voltage TOP input outpu... |
| Description |
TDA8763A; 10-bit high-speed low-power ADC
|
| File Size |
130.68K /
24 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Sanyo
|
| Part No. |
LC78836M
|
| OCR Text |
... audio data input Input is in a twos-complement MSB-first format. LR clock input CH1 is input when this pin is high, CH2 when low. Digital system power supply Clock output In 392 fs mode: outputs a 196 fs clock In other modes: outputs a clo... |
| Description |
CMOS LSI
|
| File Size |
331.87K /
12 Page |
View
it Online |
Download Datasheet
|
| |
|
 |

Analog Devices, Inc. AD[Analog Devices]
|
| Part No. |
AD1855 AD1855JRS AD1855JRSRL EVAL-AD1855EB AD1855-15
|
| OCR Text |
...s of 16, 18, 20, and 24 bits of twos complement data per channel. Digital Power Supply Connect to digital +5 V supply.
7 8 9
I O I
X2MCLK ZEROR DEEMP
10 11, 15 12 13 14 16 17 18 19 20 21 22 23 24
I I O O O O O I O I I O I I
... |
| Description |
Stereo, 96 kHz, Multibit DAC Stereo, 96 kHz, Multibit DAC SERIAL INPUT LOADING, 24-BIT DAC, PDSO28 Stereo 96 kHz Multibit DAC Stereo, 96 kHz, Multibit Sigma Delta DAC Data Sheet
|
| File Size |
231.06K /
15 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
Analog Devices Inc
|
| Part No. |
AD9430
|
| OCR Text |
...S compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V or 2.5 V CMOS logic. Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A ... |
| Description |
12-Bit, 170 MSPS/210 MSPS 3.3 V A/D Converter From old datasheet system
|
| File Size |
1,354.50K /
28 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|