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ST Microelectronics
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| Part No. |
M34D64-W
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| OCR Text |
...serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowl...way. the bus master sends from 1 to 32 bytes of data. if write control (wc ) is high, the contents o... |
| Description |
64 KBIT SERIAL I²C BUS EEPROM WITH HARDWARE WRITE CONTROL ON TOP QUARTER OF MEMORY
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| File Size |
136.12K /
21 Page |
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Motorola Mobility Holdings, Inc.
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| Part No. |
MPC7410HX400LE
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| OCR Text |
...tion queue has been extended to eight slots. there are no other significant changes to scalar pipelines, decode/dispatch/completion mechan...way set-associative branch target instruction cache (btic) for eliminating branch delay slots dis... |
| Description |
32-BIT, 400 MHz, RISC PROCESSOR, CBGA360 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
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| File Size |
678.38K /
52 Page |
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it Online |
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Atmel corp
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| Part No. |
AT75C1212NBSP AT75C1212
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| OCR Text |
...tect the DTMF signal, a bank of eight resonant band pass filters is used. The central frequency of each filter corresponds to one of the eig...way. Figure 5 describes this format. Figure 5. Request Notification Message Format
Mailbox Base Add... |
| Description |
Provides a G.723.1 voice processing and multi-way conferencing software module, including algorithms
From old datasheet system
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| File Size |
207.43K /
41 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
MPC859TMPC859DSL MPC866EC
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| OCR Text |
...ddress lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank -- Up to 30 wait states programmable per memory bank -- Glueless interface to Pa... |
| Description |
PowerQUICC™ Integrated Communications Processor
From old datasheet system
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| File Size |
463.37K /
92 Page |
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it Online |
Download Datasheet |
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Motorola Semiconductor
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| Part No. |
MPC7448
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| OCR Text |
... from the instruction stream. - Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) ...way set-associative instruction and data caches -- Pseudo least-recently-used (PLRU) replacement alg... |
| Description |
RISC Microprocessor
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| File Size |
1,433.99K /
60 Page |
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it Online |
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