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    MCNIX[Macronix International]
Part No. MX98715A
OCR Text ...ows a single RJ-45 connector to link with the other IEEE802.3uP/N:PM0537 compliant device without re-configuration. In MX98715A, an innov...transaction, these four bits provide the bus command. During the data phase, these four bits provide...
Description SINGLE CHIP FAST ETHERNET NIC CONTROLLER

File Size 211.25K  /  32 Page

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    ETC[ETC]
Part No. MX98725
OCR Text ...ows a single RJ-45 connector to link with the other IEEE802.3u-compliant device completely without any need to set configuration. In MX98725...transaction, these four bits provide the bus command. During the data phase, these four bits provide...
Description SINGLE CHIP FAST ETHERNET NIC CONTROLLER

File Size 175.79K  /  33 Page

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    Macronix International Co., Ltd.
Part No. MX98715EC MACRONIXINTERNATIONALCOLTD-MX98715EC
OCR Text ...ows a single rj-45 connector to link with the other ieee802.3u-com- pliant device without re-configuration. in mx98715ec, an innovative and ...transaction, these four bits provide the bus command. during the data phase, these four bits provide...
Description IEEE802.3u Compliant Single Chip 32-Bit Full Duplex,10/100Mbps Highly Integrated Fast Ethernet NIC Controller(符合IEEE802.3u的单片、全双工0/100Mbps 32快速以太网NIC控制 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128

File Size 153.03K  /  28 Page

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    89HPES12NT3 89HPES12NT3ZABC 89HPES12NT3ZABCG

Integrated Device Technology
Part No. 89HPES12NT3 89HPES12NT3ZABC 89HPES12NT3ZABCG
OCR Text ...n - Supports automatic per port link width negotiation (x4, x2, or x1) - Static lane reversal on all ports - Automatic polarity inversion on...transaction Layer Data link Layer transaction Layer Data link Layer transaction Layer Data Lin...
Description 12-lane 3-Port Non-Transparent PCI Express㈢ Switch

File Size 253.48K  /  29 Page

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    PLX Technology, Inc.
Part No. PEX8114-BC13BIG
OCR Text ...d status register. dl_down data link layer is down (a pci express link/port status). dllp data link layer packet (origina te at the data li...transaction semantics. pci express endpoints do not. fcp flow control packet devices on each link ...
Description PCI BUS CONTROLLER, PBGA256 17 X 17 MM , 1 MM PICTH, GREEN, PLASTIC, BGA-256

File Size 2,256.11K  /  372 Page

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    MX98725

List of Unclassifed Manufacturers
Part No. MX98725
OCR Text ...ows a single rj-45 connector to link with the other ieee802.3u-com- pliant device completely without any need to set con- figuration. in mx9...transaction, these four bits provide the bus command. during the data phase, these four bits provide...
Description SINGLE CHIP FAST ETHERNET NIC CONTROLLER

File Size 183.07K  /  33 Page

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    http://
意法半导
ST Microelectronics
Part No. MK50H25 MK50H25DIP MK50H25Q MK50H25PLCC
OCR Text link LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (M...transaction. READ is driven by the MK50H25 only while it is the BUS MASTER. READ is valid during the...
Description HIGH SPEED link LEVEL CONTROLLER

File Size 529.82K  /  64 Page

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    ST Microelectronics
Part No. MK50H28PLCC52 MK50H28Q25
OCR Text link frame relay controller section 1 - features based on itu q.933 annex a and t1.617 an- nex d standards for frame relay service and addit...transaction. read is driven by the mk50h28 only while it is the bus master. read is valid during the...
Description MULTI LOGICAL link FRAME RELAY CONTROLLER

File Size 431.87K  /  64 Page

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    PEX8311

PLX Technology
Part No. PEX8311
OCR Text ...on the destination bus. Data link Layer Packet (originates at the Data link Layer); can contain Flow Control (FCx DLLPs) acknowledge pack...transaction semantics. PCI Express endpoints do not support I/O nor Locked transaction semantics. ...
Description ExpressLane PCI Express to Generic Local Bus Bridge

File Size 3,481.67K  /  462 Page

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    PEX8311 PEX8311-AA66BCF PEX8311RDK

AVAGO TECHNOLOGIES LIMI...
PLX Technology
Part No. PEX8311 PEX8311-AA66BCF PEX8311RDK
OCR Text ...rt that operates as a single x1 link with a maximum of 250 Megabytes per second of throughput per transmit and receive directions. The singl...transaction queues for eight outstanding TLPs o VGA/ISA Enable Registers o On-the-fly Endian convers...
Description PCI Express to Generic Local Bus Bridge

File Size 1,969.68K  /  4 Page

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