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MAXIM - Dallas Semiconductor
Maxim Integrated Products, Inc.
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| Part No. |
MAX9323
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| OCR Text |
lvpecl Output Clock and Data Driver
General Description
The MAX9323 low-skew, low-jitter, clock and data driver distributes one of two single-ended lvcmos inputs to four differential lvpecl outputs. A single logic control signal (CLK_SEL)... |
| Description |
One-to-Four lvcmos-to-lvpecl Output Clock and Data Driver
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| File Size |
268.25K /
11 Page |
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Download Datasheet
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Integrated Device Techn...
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| Part No. |
ICS854S058I
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| OCR Text |
..., npclk input pairs can accept lvpecl, lvds, sstl or cml levels. the fully differential architecture and low propagation delay make it ide...lvcmos/lvttl interface levels. 9 pclk2 input pulldown non-inverting differential lvpecl clock input... |
| Description |
One differential LVDS output pair
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| File Size |
441.17K /
16 Page |
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it Online |
Download Datasheet |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS85214I ICS85214AGI ICS85214AGIL ICS85214AGILF
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| OCR Text |
...ifferential input levels: LVDS, lvpecl, HSTL, SSTL, HCSL * CLK1 can accept the following input levels: lvcmos or LVTTL * Output frequency up to 700MHz * Translates any single ended input signal to HSTL levels with resistor bias on nCLK0 inp... |
| Description |
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Low Skew, 1-to-5, Differential-to-HSTL Fanout Buffer. VOHmax=1.4V
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| File Size |
174.70K /
15 Page |
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it Online |
Download Datasheet |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS85214 ICS85214AG
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| OCR Text |
...ifferential input levels: LVDS, lvpecl, HSTL, SSTL, HCSL * CLK1 can accept the following input levels: lvcmos or LVTTL * Output frequency up to 700MHz * Translates any single ended input signal to HSTL levels with resistor bias on nCLK0 inp... |
| Description |
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Low Skew, 1-to-5, Differential-to- HSTL Fanout Buffer. VOHmax=1.4V
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| File Size |
105.82K /
16 Page |
View
it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
ICS854S057BI
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| OCR Text |
...ing differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: >2ghz ? part-to-part skew: 200ps (maximum) ? propagation...lvcmos/lvttl interface levels. 7 pclk1 input non-inverting lvpecl differential clock input. r t = 5... |
| Description |
One LVDS output pair
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| File Size |
705.54K /
15 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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