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Cypress
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Part No. |
CY7C1302V25 7C1302V25
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OCR Text |
...ll accesses * Double Data Rate (ddr) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz * Two input clocks (K and ...qdr architecture consists of two separate ports to access the memory array. The Read port has dedica... |
Description |
9-Mb Pipelined SRAM with qdr?Architecture From old datasheet system
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File Size |
249.54K /
23 Page |
View
it Online |
Download Datasheet |
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Cypress
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Part No. |
CY7C1304V25 7C1304V25
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OCR Text |
...s frequency * Double Data Rate (ddr) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz * Two input clocks (K and ...qdr architecture. qdr architecture consists of two separate ports to access the memory array. The Re... |
Description |
9-Mb Pipelined SRAM with qdr?Architecture From old datasheet system
|
File Size |
215.62K /
23 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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