| |
|
 |
|
| Part No. |
IBM041841QLAD-6
|
| OCR Text |
...he sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore, triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k... |
| Description |
256K X 18 STANDARD SRAM, 3 ns, PBGA119
|
| File Size |
171.10K /
23 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
INTEGRATED SILICON SOLUTION INC
|
| Part No. |
IS61LPS25632T-200TQI
|
| OCR Text |
... (i/o) auto power-down during deselect single cycle deselect snooze mode for reduced-power standby jtag boundary scan for pbga package t version (three chips selects) d version (two chips selects) j version (pbga package with ... |
| Description |
256K X 32 CACHE SRAM, 3.1 ns, PQFP100
|
| File Size |
176.18K /
29 Page |
View
it Online |
Download Datasheet |
| |
|
|
ALLIANCE SEMICONDUCTOR CORP
|
| Part No. |
AS7C33128NTD36A-100BC AS7C33128NTD36A-166TQC
|
| OCR Text |
...in pipelined mode, a two-cycle deselect latency allows pending read or write operations to be completed. use the adv/ld (burst advance) input to perform burst read, write, and deselect operations. when adv/ld is high, external addresse... |
| Description |
128K X 36 ZBT SRAM, 12 ns, PQFP100
128K X 36 ZBT SRAM, 9 ns, PQFP100
|
| File Size |
161.04K /
10 Page |
View
it Online |
Download Datasheet |
| |
|
|
ALLIANCE SEMICONDUCTOR CORP
|
| Part No. |
AS7C33256NTD18A-183TQC
|
| OCR Text |
... in pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed. use the adv (burst advance) input to perform burst read, write and deselect operations. when adv is high, external addresses, chip ... |
| Description |
256K X 18 ZBT SRAM, 9 ns, PQFP100
|
| File Size |
235.40K /
10 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
IBM0436A41BLAB-3
|
| OCR Text |
...he sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high- z, therefore triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k... |
| Description |
128K X 36 STANDARD SRAM, 1.7 ns, PBGA119
|
| File Size |
142.68K /
25 Page |
View
it Online |
Download Datasheet |
| |
|
|
ALLIANCE SEMICONDUCTOR CORP
INTEGRATED SILICON SOLUTION INC
|
| Part No. |
AS7C33256NTD18A-100TQI AS7C33256NTD18A-133TQI AS7C33256NTD16A-133TQC AS7C33256NTD16A-100TQC
|
| OCR Text |
...i n pipelined mode, a two-cycle deselect latency allows pendin g read or write operations to be completed. use the adv (burst advance) input to perform burst read, write, and deselect operations. when adv is high, external addresses, chip ... |
| Description |
256K X 18 ZBT SRAM, 12 ns, PQFP100
256K X 18 ZBT SRAM, 10 ns, PQFP100
256K X 16 ZBT SRAM, 10 ns, PQFP100
256K X 16 ZBT SRAM, 12 ns, PQFP100
|
| File Size |
162.82K /
10 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
