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For fbk Found Datasheets File :: 213 Search Time::2.156ms
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				Integrated Circuit Systems
Part No.	ICS1523M
OCR Text	.../W Bit Name PDen PD_Pol Ref_Pol fbk_Pol fbk_Sel Func_Sel EnPLS EnDLS 1h Loop Control R/W* PFD0-2 Reserved PSD0-1 Reserved 2h 3h FdBk Div 0 FdBk Div 1 R/W* R/W* FBD0-7 FBD8-11 Reserved 4h DPA Offset R/W DPA_OS0-5 Reserved Fil_Sel 5h DPA Cont...
Description	High-Performance Programmable Line-Locked Clock Generator
File Size	1,118.41K / 27 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC
Part No.	23S08-1DC 23S08-1DC8
OCR Text	...utput bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1x, 2x, 4x output options (see table): ? idt23s08-1 1x ? idt23s08-2 1x, 2x ? idt23s...
Description	23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
File Size	72.65K / 10 Page	View it Online	Download Datasheet

				MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP
Part No.	LX1810-CDBT
OCR Text	.... -0.3 v to 15v sleep, status, fbk+, fbk- ........................................................... -0.3v to v dd +0.3v is- ..............................................................................................pv dd ?2 to pv d...
Description	FB BASED PRPHL DRVR WITH PWM, PDSO28
File Size	122.42K / 6 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC
Part No.	2308B-2DCI8
OCR Text	...utput bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1x, 2x, 4x output options (see available options table) ? no external rc network req...
Description	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
File Size	284.55K / 17 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... Integrated Circuit Systems
Part No.	ICS1522M ICS1522
OCR Text	...xternal video sources. When the fbk_SEL bit is set to logic 0, the phasefrequency detector will use the EXTfbk pin as its feedback input. The loop phase will be locked to the rising edges of the signal applied to the EXTfbk input if fbk_POL...
Description	User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator 用户可编程视频时钟发生器/线锁定时钟再
File Size	363.37K / 13 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC
Part No.	2308A-4DCI
OCR Text	...utput bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1x, 2x, 4x output options (see table): ? idt2308a-1 1x ? idt2308a-2 1x, 2x ? idt230...
Description	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
File Size	101.37K / 10 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC
Part No.	IDT2308-1HDCG8
OCR Text	...utput bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1x, 2x, 4x output options (see table): ? idt2308-1 1x ? idt2308-2 1x, 2x ? idt2308-...
Description	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
File Size	196.64K / 13 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	CY23FP12 CY23FP12OXC CY23FP12OXCT CY23FP12OXI CY23FP12OXIT CY3692 CY23FP12OC CY23FP12OCT CY23FP12OI CY23FP12OIT CY3672
OCR Text	... CLKA1 CLKA2 CLKA3 REFSEL fbk CLKA0 CLKA1 VSSA CLKA2 CLKA3 VDDA VSSA CLKA4 CLKA5 VDDA VSSC S1 REFSEL REF1 REF2 fbk /M /N 100 to 400MHz PLL /1 /2 /3 /4 /X CLKA4 CLKA5 VSSA VDDB CLKB0 CLKB1 CLKB2 CLKB3 Test Logic S[2:1] VSSC...
Description	200-MHz Field Programmable Zero Delay Buffer
File Size	199.21K / 10 Page	View it Online	Download Datasheet

				INTEGRATED DEVICE TECHNOLOGY INC
Part No.	IDT2308-2HDCGI8 IDT2308-2HDCG8
OCR Text	...utput bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1x, 2x, 4x output options (see table): ? idt2308-1 1x ? idt2308-2 1x, 2x ? idt2308-...
Description	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
File Size	160.71K / 13 Page	View it Online	Download Datasheet

For fbk Found Datasheets File :: 213 Search Time::2.156ms
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