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				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	PCK953BD PCK953
OCR Text	...ents. All control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 transmission lines. For series terminated 50 lines, each of the PCK953 outputs can drive tw...
Description	50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver
File Size	65.55K / 8 Page	View it Online	Download Datasheet

				Vectron International, Inc
Part No.	FX-400 FX-40011
OCR Text	...o 4 ext.-muxed clock inputs ? lvcmos / lvds / lvpecl inputs compatible ? di" erential lvpecl /lvds or lvcmos output ? lock detect / loss...to 80% of a full output swing (fig 3). 5. not tested in production, guaranteed by design, veri ed ...
Description	Low Jitter Frequency Translator
File Size	620.58K / 10 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS843004 ICS843004AG ICS843004AGT
OCR Text	...crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz,...to 85C ambient operating temperature GENERAL DESCRIPTION The ICS843004 is a 4 output LVPECL synt...
Description	FEMTOCLOCKS LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER FEMTOCLOCKS⑩ LVCMOS/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
File Size	288.06K / 16 Page	View it Online	Download Datasheet

				Hynix
Part No.	HY5MS7B2BLF
OCR Text	...age levels are compatible with lvcmos. read and write accesses to the low power ddr sdram (mob ile ddr sdram) are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed se...
Description	Mobile DDR SDRAM 512M
File Size	1,600.75K / 61 Page	View it Online	Download Datasheet

				Analog Devices http://
Part No.	AD9573-EVALZ AD9573ARUZ
OCR Text	...os for 100 mhz, 33.33 mhz lvds/lvcmos output format integrated loop filter space saving 4.4 mm 5.0 mm tssop 0.235 w power dissipation ...to maximize line card performance. other applications with demanding phase noise and jitter requir...
Description	PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs
File Size	212.01K / 12 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... ICST[Integrated Circuit Systems] NXP Semiconductors N.V. DOMINANT Opto Technologies Sdn. Bhd.
Part No.	ICSSSTV16857 ICSSSTV16857YL-T ICS16857 ICSSSTV16857YG-T ICSSSTV16857YGLF-T
OCR Text	...t for the RESET# input which is LVCMOS. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supporte...
Description	SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 0.240 INCH, 0.50 MM PITCH, TSSOP-48 DDR 14-Bit Registered Buffer 复员14位注册缓冲区
File Size	112.85K / 8 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICSSSTV16859 ICSSSTV16859YK
OCR Text	...t for the RESET# input which is LVCMOS. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supporte...
Description	DDR 13-Bit to 26-Bit Registered Buffer
File Size	231.88K / 8 Page	View it Online	Download Datasheet

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