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Freescale
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Part No. |
MC56F8355MC56F8155NBSP MC56F8355
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OCR Text |
...IPAB
IPWDB
IPRDB
Clock resets
P System O Integration R Module
PLL
* EMI not functional in this package; use as GPIO pins
SPI0 or GPIOE 4
SCI1 or GPIOD
2
SCI0 or GPIOE
2
COP/ Watchdog
Interrupt Controller
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Description |
16-Bit Microcontrollers From old datasheet system
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File Size |
883.13K /
164 Page |
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it Online |
Download Datasheet
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OKI
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Part No. |
MSM6502B MSM6512 MSM6502B_MSM6512
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OCR Text |
...g operations automatically: (1) resets all bits of the PC (program counter) to"0". (2) Sets all bits of the parallel I/O ports (P0.0 to P1.3) to "1" (3) resets the internal register (H, L, ACC, C, P3, P4, P5). (4) resets the skip flag. (5) ... |
Description |
Low-power and Built-in LCD Driver 4-Bit Microcontroller From old datasheet system
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File Size |
114.68K /
12 Page |
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it Online |
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LAPIS SEMICONDUCTOR CO LTD
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Part No. |
MSM6512-XXXGS-2K
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OCR Text |
...perations automatically: (1) resets all bits of the pc (program counter) to"0". (2) sets all bits of the parallel i/o ports (p0.0 to p1.3) to "1" (3) resets the internal register (h, l, a cc , c, p3, p4, p5). (4) resets the skip... |
Description |
4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP56
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File Size |
173.29K /
13 Page |
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it Online |
Download Datasheet
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IDT
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Part No. |
IDT74LVCH16701A 74LVCH16701A_DS_20952
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OCR Text |
...he FIFO are inhibited. CLK also resets the FIFO when RESET is low. Enable pin for FIFO input clock (Active LOW) Enable pin for FIFO output clock (Active LOW) Write path FIFO full flag. Goes low when FIFO is full. Synchronous FIFO reset - wh... |
Description |
3.3V CMOS 18-BIT READ/WRITE BUFFER From old datasheet system
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File Size |
79.96K /
8 Page |
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it Online |
Download Datasheet
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Price and Availability
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