| Description |
128 x 64 pixel format, LED or EL Backlight available 128k x 8 STANDARD sram, 20 ns, PDSO32
High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 128k x 8 STANDARD sram, 12 ns, PDSO32
5V 128k x 8 CMOS sram (Center power and ground) 128k x 8 STANDARD sram, 20 ns, PDSO32
5V 128k x 8 CMOS sram (Center power and ground) 128k x 8 STANDARD sram, 15 ns, PDSO32
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125
sram - 5V Fast asynchronous
|
View
it Online
Download Datasheet
