| |
|
 |
Mitel Networks, Corp.
|
| Part No. |
MT9041BP
|
| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the mt9041b generates st-bus clock and framing signals that are phase locked to either a 2.04... |
| Description |
T1/E1 System Synchronizer T1/E1的系统同
|
| File Size |
76.88K /
19 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Zarlink Semiconductor, Inc.
|
| Part No. |
ZL50010GDG2
|
| OCR Text |
...ated digital phase-locked loop (dpll) meets telcordia gr-1244-core stratum 4 enhanced specifications ? dpll provides automatic reference switching, jitter attenuation, holdover and free run functions ? per-stream st-bus input with data ... |
| Description |
Flexible 512 Channel DX with Enhanced DPLL TELECOM, DIGITAL TIME SWITCH, PBGA144
|
| File Size |
706.45K /
87 Page |
View
it Online |
Download Datasheet |
| |
|
|
Zarlink Semiconductor, Inc.
|
| Part No. |
ZL30110
|
| OCR Text |
...ystal or oscillator ? provides dpll lock and reference fail indication ? automatic free run mode on reference fail ? dpll bandwidth of 922 hz for all rates of input reference and 58 hz for an 8 khz input reference ? less than 5 psec rms ... |
| Description |
Telecom Rate Conversion DPLL 电信速率转换数字锁相
|
| File Size |
262.53K /
21 Page |
View
it Online |
Download Datasheet |
| |
|
|
STMicroelectronics N.V.
|
| Part No. |
STSLVDSP27
|
| OCR Text |
...ntial line drivers and embedded dpll features sub-low voltage differential signaling: v od = 150mv with r t = 100 , c l = 10pf clock range: 4 to 27 mhz in parallel mode, byp = gnd operative frequency serial mode, byp = v dd ; din... |
| Description |
8-bit low voltage serializer with 1.8V high speed dual differential line drivers and embedded DPLL 8位串行的低电压与1.8V高速双差分线路驱动器和嵌入式数字锁相环
|
| File Size |
313.92K /
23 Page |
View
it Online |
Download Datasheet |
| |
|
|
STMicroelectronics N.V.
|
| Part No. |
STLC7545
|
| OCR Text |
...hase locked loops - separate tx dpll and rx dpll - terminal clock input for tx synchronizationon all multiples of 2400hz (vfast synchronization mode) or on sub-multiple of baud rate (7544 synchronization mode) - bit, baud, sampling and high... |
| Description |
Enhanced V.34 BIS Analog Front-End(单片模拟前端) 国际清算银行增强.34模拟前端（单片模拟前端）
|
| File Size |
389.15K /
53 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
