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pmc
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| Part No. |
1991797
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| OCR Text |
............................... 10 implementing DS-1/0 CARDS WITH PROTECTION ...................... 12
4
FABRIC ARCHITECTURES ............................................................................................ 14 4.1 SINGLE STAG... |
| Description |
From old datasheet system
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| File Size |
434.58K /
54 Page |
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it Online |
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Xilinx
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| Part No. |
XCR5064 DS043
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| OCR Text |
...nal sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing DS043 (v1.3... |
| Description |
Product Specification
From old datasheet system
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| File Size |
250.17K /
14 Page |
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it Online |
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Xilinx
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| Part No. |
XCR3320 DS033
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| OCR Text |
...nal sense amplifier methods for implementing product terms (a technique that has been used since the bipolar era) with a cascaded chain of pure CMOS gates, both standby and dynamic power are dramatically reduced when compared to other CPLDs... |
| Description |
Product Specification
From old datasheet system
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| File Size |
362.82K /
43 Page |
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it Online |
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Xilinx
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| Part No. |
XCR5128C DS042
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| OCR Text |
...nal sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These... |
| Description |
with Enhanced Clocking
From old datasheet system
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| File Size |
338.66K /
19 Page |
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it Online |
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STMicroelectronics N.V.
Atmel Corp
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| Part No. |
AT40K05 AT40K05LV AT40K10LV AT40K20LV AT40K40LV
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| OCR Text |
...(DSP/processorbased) designs by implementing a variety of computation intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosin... |
| Description |
AT40K05/10/20/40(LV) Summary [Updated 5/02. 4 Pages] 5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam. AT40K05/10/20/40（吕）摘要[更新5 / 024页] 5K - 5万门的FPGA与DSP优化的核心细胞和分布式FreeRam
From old datasheet system
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| File Size |
54.84K /
4 Page |
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it Online |
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Price and Availability
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