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asychronous Datasheet PDF File

For asychronous Found Datasheets File :: 125 Search Time::0.688ms
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				Integrated Circuit Syst... ICST[Integrated Circuit Systems]
Part No.	ICS9150-08 ICS9150F-08
OCR Text	... Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9150-08. All other clocks will continue to run while the CPUCLKs are...
Description	Frequency Generator & Integrated Buffers for Pentium/Pro? Frequency Generator & Integrated Buffers for Pentium/Pro⑩
File Size	426.89K / 13 Page	View it Online	Download Datasheet

				Integrated Device Techn... IDT[Integrated Device Technology] Integrated Device Technology, Inc.
Part No.	IDT70121 IDT70121L IDT70121L25J IDT70121L35J IDT70121L45J IDT70121L55J IDT70121S IDT70121S25J IDT70121S35J IDT70121S45J IDT70121S55J IDT70125L IDT70125L25J IDT70125L35J IDT70125L45J IDT70125L55J IDT70125S IDT70125S25J IDT70125S35J IDT70125S45J IDT70125S55J
OCR Text	...p.) Standby: 1mW (typ.) * Fully asychronous operation from either port * MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip * On-chip port arbitration logic (IDT70121 only) * BUSY output flag on Maste...
Description	HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT Low-Power JFET-Input Operational Amplifier 8-SOIC 0 to 70 高K × 9双端口静态RAM繁忙
File Size	169.14K / 12 Page	View it Online	Download Datasheet

				Electronic Theatre Controls, Inc. ETC[ETC] Micro Analog systems
Part No.	MAS7838 MAS7838N MAS7838S MAS7838S-T
OCR Text	... internal timing signal for the asychronous circuits. This internal timing signal (16T) is 16 times the TXC bit rate in order to sample the asynchronous data stream (TDI) at the proper speed. Timing Circuits 16 x TXC MAS 7838 TXC ...
Description	SYNCHRONOUS TO ASYNCHRONOUS CONVERTER SAC CMOS 转炉同步的异步国资委的CMOS
File Size	110.05K / 9 Page	View it Online	Download Datasheet

				PERICOM[Pericom Semiconductor Corporation]
Part No.	PI6C106
OCR Text	...ing Diagram CPUS_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be ...
Description	Pentium/Pro System Clock Chip
File Size	324.40K / 8 Page	View it Online	Download Datasheet

				Intersil, Corp. INTERSIL[Intersil Corporation]
Part No.	MD82C284-12_883 82C284883 82C284_883 MD82C284-12/883 82C284/883
OCR Text	.../883 as possible. 3. This is an asychronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge. 4. The pull-up resistor value for the READY pin is 620 with the rated 150pF load. 5. t16...
Description	Clock Generator and Ready Interface for 80C286 Processors 时钟发生器和Ready接口80C286处理 Clock Generator and Ready Interface for 80C286, CMOS, 883 Compliant, 10MHz
File Size	160.00K / 9 Page	View it Online	Download Datasheet

				ETC
Part No.	MAS9138
OCR Text	... internal timing signal for the asychronous circuits. This internal timing signal (16T) is 16 times the TXC bit rate in order to sample the asynchronous data stream (TDI) at the Timing Circuits 16 x TXC DA9138/40.002 November 1, 1997 ...
Description	ASYNCHRONOUS TO SYNCHRONOUS CONVERTER
File Size	145.35K / 11 Page	View it Online	Download Datasheet

				ICS
Part No.	ICS9248-50
OCR Text	... Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-50. The minimum that the CPUCLK is enabled (CPU_STOP# high puls...
Description	CK100 Main Clock for BX Mobile, Supports 66.6 - 100MHz
File Size	239.65K / 10 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-95
OCR Text	...Timing Diagram CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-95. The minimum that the CPU clock is enabled (CPU_STOP# hig...
Description	Frequency Generator & Integrated Buffers for PENTIUM/ProTM Single Chip MVP4 Clock
File Size	296.48K / 16 Page	View it Online	Download Datasheet

				ICS
Part No.	ICS9250-09
OCR Text	...s are held at a Low state. This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0" when driven active(Low). Does not affect the CPU/2 clocks. This asynchronous input halts the PCICLK[1:7] at logic"0" when driven a...
Description	CK820 Single Chip Clock, Supports 100 - 133MHz
File Size	250.57K / 12 Page	View it Online	Download Datasheet

				TE Connectivity, Ltd. Integrated Device Technology, Inc. ICST[Integrated Circuit Systems]
Part No.	ICS9248-56 ICS9248YG-56-T ICS9248YG-56LF-T ICS9248F-56
OCR Text	... Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-56. The minimum that the CPUCLK is enabled (CPU_STOP# high puls...
Description	Peripheral IC 外围芯片 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 4.40 MM, 0.65 MM PITCH, TSSOP-28 20-Bit Buffers/Drivers With 3-State Outputs 56-TSSOP -40 to 85 Frequency Generator & Integrated Buffers Frequency Timing Generator for Pentium II Systems BX Mobile Main Clock with Real Time Spread, Supports 66.6 - 100MHz
File Size	262.48K / 11 Page	View it Online	Download Datasheet

For asychronous Found Datasheets File :: 125 Search Time::0.688ms
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