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For awaretm-designed Found Datasheets File :: 48 Search Time::1.734ms
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					Cypress Semiconductor
Part No.	CY29350AI CY29350AIT CY29350
OCR Text	...d loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9350 Industrial temperature range: -40C to +85C 32-pin ...designed for high speed clock distribution applications. The CY29350 features Xtal and LVCMOS refere...
Description	2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
File Size	182.70K / 7 Page	View it Online	Download Datasheet

					CYPRESS[Cypress Semiconductor]
Part No.	CY29351AI CY29351AIT CY29351
OCR Text	...d loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9351 Industrial temperature range: -40C to +85C 32-Pin ...designed for high speed clock distribution applications. The CY29351 features LVPECL and LVCMOS refe...
Description	2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
File Size	284.36K / 8 Page	View it Online	Download Datasheet

					Cypress Semiconductor
Part No.	CY29775AI CY29775AIT CY29775AXI CY29775AXIT CY29775
OCR Text	...put skew PLL bypass mode Spread AwareTM Output enable/disable Industrial temperature range: -40C to +85C 52-Pin 1.0-mm TQFP package Block Diagram V C O _S E L(1,0) P LL_E N TCLK_SEL T C LK 0 TC LK1 F B _IN PLL 200 5 0 0M H z /2 /4 /2 /...
Description	2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
File Size	192.52K / 11 Page	View it Online	Download Datasheet

					Cypress Semiconductor
Part No.	CY28352 CY28352OC CY28352OCT CY28352OXC CY28352OXCT
OCR Text	... to DDRI specification * Spread AwareTM for electromagnetic interference (EMI) reduction * 28-pin SSOP package Description This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels. This device ...
Description	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
File Size	113.95K / 8 Page	View it Online	Download Datasheet

					Cypress Semiconductor
Part No.	CY2SSTV850 CY2SSTV850OC CY2SSTV850ZC CY2SSTV850ZCT CY2SSTV850OCT
OCR Text	... the clock input * SSCG: Spread AwareTM for EMI reduction * 48-pin SSOP and TSSOP packages * Conforms to JEDEC JC40 and JC42.5 DDR specifications Description This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and diffe...
Description	Differential Clock Buffer/Driver
File Size	111.43K / 11 Page	View it Online	Download Datasheet

					Cypress Semiconductor Corp.
Part No.	CY29774 CY29774AI CY29774AIT
OCR Text	...put skew PLL bypass mode Spread AwareTM Output enable/disable Pin compatible with MPC9774 Industrial temperature range: -40C to +85C 52-Pin ...designed for high-speed clock distribution applications. Block Diagram Pin Configuration V ...
Description	Clocks and Buffers : Clock Distribution 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14杈???跺欢杩???插?) 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14输出零延迟缓冲器)
File Size	72.34K / 9 Page	View it Online	Download Datasheet

					Cypress Semiconductor Corp.
Part No.	CY29653 CY29653AIT CY29653AC CY29653ACT CY29653AI
OCR Text	...loop (PLL) bypass mode * Spread AwareTM * Output enable/disable * Pin-compatible with MPC9653 and MPC953 * Industrial temperature range: -40...designed for high-speed clock distribution applications. The CY29653 features an LVPECL reference cl...
Description	3.3V 125-MHz 8-Output Zero Delay Buffer(3.3V, 125MHz, 8输出零延迟缓冲器)
File Size	193.81K / 7 Page	View it Online	Download Datasheet

					Cypress Semiconductor
Part No.	CY29658 CY29658AI CY29658AIT
OCR Text	...d loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9658 and MPC958 Industrial temperature range: -40C to +...designed for high-speed clock distribution applications. The CY29658 features an LVPECL reference cl...
Description	2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
File Size	100.97K / 7 Page	View it Online	Download Datasheet

					ETC[ETC] SpectraLinear Inc
Part No.	CY28352 CY28352OXC CY28352OXCT CY28352OCT CY28352OC
OCR Text	... to DDRI specification * Spread AwareTM for electromagnetic interference (EMI) reduction * 28-pin SSOP package Description This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels. This device ...
Description	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
File Size	114.29K / 7 Page	View it Online	Download Datasheet

					CYPRESS SEMICONDUCTOR CORP
Part No.	CY29772 CY29772AI CY29772AIT
OCR Text	...d loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9772 and MPC972 Industrial temperature range: -40C to +...designed for high-speed clock-distribution applications. The CY29772 features one on-chip crystal os...
Description	2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
File Size	90.20K / 12 Page	View it Online	Download Datasheet

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