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ICS
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| Part No. |
MK2049-36
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| OCR Text |
Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications frequencies. This allows for the genera... |
| Description |
3.3 Volt Communications Clock PLL
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| File Size |
76.13K /
7 Page |
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Zarlink
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| Part No. |
ZL30406
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| OCR Text |
...406
The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and... |
| Description |
SONET/SDH Clock Multiplier PLL
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| File Size |
232.64K /
20 Page |
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it Online |
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Zarlink
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| Part No. |
ZL30414
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| OCR Text |
...ion
The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30414 is shown ... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
220.94K /
23 Page |
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Download Datasheet |
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zarlink
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| Part No. |
ZL30416
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| OCR Text |
...ion
The ZL30416 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30416 is shown ... |
| Description |
SONET/SDH Clock Multiplier PLL
From old datasheet system
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| File Size |
330.43K /
22 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
SP5611 304
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| OCR Text |
...mmable divider is frequency and phased locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an onchip crystal controlled oscillator. The compariso... |
| Description |
1・3GHz Bidirectional I2C Bus Controlled Synthesiser
From old datasheet system
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| File Size |
494.60K /
12 Page |
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it Online |
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