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INTEGRATED DEVICE TECHNOLOGY INC
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Part No. |
EE801NDGI8
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OCR Text |
...fective value of 4pf. reference pre-divider, reference divider, feedback-divider and post-divider each pll incorporates an 8-bit reference-...configured to support an lvds output. for lvds support, vddo1 must be set to 3.3v. vddo1 must have ... |
Description |
VIDEO CLOCK GENERATOR, QCC24
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File Size |
240.67K /
27 Page |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C924DX-AI CY7C924DX-AC
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OCR Text |
...ncoder/decoder 10- or 12-bit pre-encoded data path (raw mode) 8- or 10-bit encoded data transport (using 8b/10b coding) parity check...configured as either a fifo (configurable for utopia emulation or for depth expan- sion through exte... |
Description |
Fiber-Optic Transceiver 光纤收发
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File Size |
1,138.82K /
58 Page |
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Lattice Semiconductor, Corp. LATTICE SEMICONDUCTOR CORP
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Part No. |
LFE3-95EA-6FN672C LFE3-95EA-8FN672C LFE3-150EA-7FN672ITW LFE3-95E-7FN1156C LFE3-70E-8FN1156I LFE3-70EA-8FN484I LFE3-150EA-6FN672ITW LFE3-150EA-8FN672CTW LFE3-150EA-6FN1156C LFE3-35EA-7FTN256I
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OCR Text |
...and up to ten plls per device ? pre-engineered source synchronous i/o ? ddr registers in i/o cells ? dedicated read/write levelling function...configured to support an array of popular data protocols including pci express, smpte, ethernet (xa... |
Description |
FPGA, 375 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672 FPGA, 500 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672 FPGA, 420 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672 Field Programmable Gate Arrays - FPGAs 92K LUTs, 490 I/O 7 Speed FPGA, 420 MHz, PBGA1156 Field Programmable Gate Arrays - FPGAs 66.5K LUTs, 490 I/O 8 Speed FPGA, 500 MHz, PBGA1156 FPGA, 500 MHz, PBGA484 23 X 23 MM, LEAD FREE, FPBGA-484 FPGA, 375 MHz, PBGA1156 FPGA, PBGA256
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File Size |
2,549.28K /
130 Page |
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ICS
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Part No. |
MK1575-01
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OCR Text |
...efer to the MK2069 products.
pre-configured Input/Output Frequency Combinations:
Telecom T/E Clock Modes (rising edge aligned):
Addr FS2:0
000 001 010 011
Input Clock
8 kHz 8 kHz 8 kHz 8 kHz
Output Clocks (MHz) CLK1 CLK2
3.0... |
Description |
Low Cost Clock Recovery PLL
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File Size |
127.56K /
12 Page |
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Cypress
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Part No. |
CY7C924DX 7C924DX
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OCR Text |
PRELIMINARY
CY7C924DX
200-MBaud HOTLink(R) Transceiver
Features
* Second-generation HOTLink(R) technology * Fibre Channel and ESCON(...configured to accept either 8- or 10-bit data characters on each clock cycle, and stores the paralle... |
Description |
200-MBaud HOTLink Transceiver From old datasheet system
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File Size |
634.17K /
58 Page |
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it Online |
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Price and Availability
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