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For sampled-data Found Datasheets File :: 14016 Search Time::2.109ms
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				STMicroelectronics N.V. 意法半导 STMICROELECTRONICS[STMicroelectronics] N.A. ST Microelectronics
Part No.	M2764A M2764A-2F1 M2764A-3F1 M2764AF1 M27256F6 M27256-1F1 M27256-1F6 M27256-20F1 M27256-20F6 M27256-25F1 M27256-25F6 M27256-2F1 M27256-2F6 M27256-3F1 M27256-3F6 M27256-4F1 M27256-4F6 M27256F1
OCR Text	...Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A12 tAVQV E tGLQV G tELQV Q0-Q7 VALID tAXQX tEHQZ tGHQZ Hi-Z DATA OUT AI00778 4/10 M2764A Table 6. Read Mode DC Char...
Description	NMOS 64K 8K x 8 UV EPROM NMOS4KK的8紫外线存储器 NMOS 256K 32K x 8 UV EPROM NMOS 64K (8K x 8) UV EPROM
File Size	107.86K / 10 Page	View it Online	Download Datasheet

				Motorola, Inc MOTOROLA[Motorola Inc]
Part No.	MC12439 MC12439FN
OCR Text	... registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW, thus the parallel data must be stable on...
Description	HIGH FREQUENCY PLL CLOCK GENERATOR
File Size	129.32K / 11 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1425V18-167BZC CY7C1425V18-200BZC CY7C1425V18-250BZC CY7C1414V18
OCR Text	...C1414V18 Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1410V18 - D[7:0] CY7C1425V18 - D[8:0] CY7C1412V18 - D[17:0] CY7C1414V18 - D[35:0] Write Port Select, active LOW. Sampled on the ...
Description	36-Mbit QDR-II(TM) SRAM 2-Word Burst Architecture 36-Mbit QDR-II?? SRAM 2-Word Burst Architecture
File Size	270.30K / 23 Page	View it Online	Download Datasheet

				MICROCHIP[Microchip Technology]
Part No.	MCP3221A5T-E_OT MCP3221A5T-I_OT MCP3221A4T-E_OT MCP3221A4T-I_OT MCP3221A7T-I_OT MCP3221 MCP3221A0T-E_OT MCP3221A0T-I_OT MCP3221A1T-E_OT MCP3221A1T-I_OT MCP3221A2T-E_OT MCP3221A2T-I_OT MCP3221A3T-E_OT MCP3221A3T-I_OT MCP3221A6T-E_OT MCP3221A6T-I_OT MCP3221A7T-E_OT MCP3221A4T-E/OT MCP3221A3T-E/OT MCP3221A3T-I/OT MCP3221A2T-E/OT MCP3221A2T-I/OT MCP3221A0T-E/OT MCP3221A7T-E/OT MCP3221A7T-I/OT MCP3221A4T-I/OT
OCR Text	... This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tAC...Data input setup time STOP condition setup time STOP condition hold time Output valid from clock Bus...
Description	Low Power 12-Bit A/D Converter With I2C Interface Low Power 12-Bit A/D Converter With I2C??Interface Low Power 12-Bit A/D Converter With I2C⑩ Interface
File Size	506.06K / 27 Page	View it Online	Download Datasheet

				Cypress
Part No.	CY7C1444AV33-1XWI
OCR Text	... one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are ...data pins. oe is masked during the first clock of a read cycle when emerging fr om a deselected st...
Description	36-Mbit (1 M 36) Pipelined DCD Sync SRAM
File Size	448.49K / 24 Page	View it Online	Download Datasheet

				Alliance Semiconductor
Part No.	AS7C3364PFS32A-133TQC AS7C3364PFS32A-133TQI
OCR Text	... address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation the data accessed by the current address, registered in the address registers by the positive e...
Description	3V 64K x 8/512K x 32 pipeline burst synchronous SRAM, 133MHz
File Size	217.45K / 11 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NBC12439 NBC12439FA NBC12439FAR2 NBC12439FN NBC12439FNR2
OCR Text	... registers. Data from S_DATA is sampled on the rising edge. This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this signal is LOW; therefore, the parallel data must be sta...
Description	3.3 V/5 V Programmable PLL Synthesized Clock Generator
File Size	143.17K / 20 Page	View it Online	Download Datasheet

				Emerging Memory & Logic Solutions Inc
Part No.	EMD56164P EMD56164P-60 EMD56164P-75
OCR Text	...s and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived ...
Description	256M: 16M x 16 Mobile DDR SDRAM
File Size	768.18K / 45 Page	View it Online	Download Datasheet

				Emerging Memory & Logic Solutions Inc
Part No.	EMD56324P-60 EMD56324P-75 EMD56324P
OCR Text	...s and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived ...
Description	256M: 8M x 32 Mobile DDR SDRAM
File Size	768.11K / 45 Page	View it Online	Download Datasheet

				Eorex Corporation
Part No.	EM44AM1684LBA-37F EM44BM1684LBA-37FE EM44AM1684LBA-37FE EM448M1684LBA-37FE EM44AM1684LBA-3F EM44BM1684LBA-3FE EM44AM1684LBA-3FE EM448M1684LBA-3FE EM44AM1684LBA-5F EM44BM1684LBA-5FE EM44AM1684LBA-5FE EM448M1684LBA-5FE EM44AM1684LBA
OCR Text	...s and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). (Chip Select) All commands are masked ...
Description	256Mb (4M】4Bank】16) Double DATA RATE 2 SDRAM
File Size	492.76K / 29 Page	View it Online	Download Datasheet

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