two-stage pdf Datasheet P4 Full Text Search --- IC-ON-LINE


	Part Number	Hot Search : 00SER 4LVX1 1N4729A PDCS6112 MY50A 58009 85L02H VLDS1235
	Product Description
	Full Text Search

two-stage Datasheet PDF File

For two-stage Found Datasheets File :: 17296 Search Time::1.453ms
Page :: | 1 | 2 | 3 | <4> | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |

				NEC Corp. NEC[NEC]
Part No.	UPD16650 UPD16650N MPD16650N-TCP MPD16650N-TAB UPD16650N-XXX
OCR Text	... range: \|VEE1 - VEE2\| = 10 V) * Two acceptable CMOS input levels (3.3 and 5 V) * Output enable function * MC-selectable output count (MC = h...stage if a cascade connection is used. In the 120-output mode, the start pulse is output at the nega...
Description	120-/128-OUTPUT TFT-LCD GATE DRIVER 120-/128-OUTPUT的TFT - LCD栅极驱动 Interface IC
File Size	60.27K / 12 Page	View it Online	Download Datasheet

				NEC[NEC]
Part No.	UPD16654 UPD16654N
OCR Text	...company. Be sure to avoid using two or more packaging methods at a time. Reference NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E) 12 PD16654 [MEMO] 13 ...
Description	150/154 OUTPUT TFT-LCD GATE DRIVE
File Size	70.08K / 16 Page	View it Online	Download Datasheet

				NEC Corp. NEC[NEC]
Part No.	UPD16655 UPD16655N UPD16655N-XXX
OCR Text	... PD16655 at the next stage when two or more PD16655s are connected in cascade. The pulse is output at the falling edge of the 240th clock of shift clock CLK, and is cleared at the falling edge of the 241st clock. R,/L = "H" (right shift): ...
Description	LIQUID CRYSTAL DISPLAY DRIVER, UUC251 LCD Display Driver 240-OUTPUT TFT-LCD GATE DRIVER
File Size	69.71K / 12 Page	View it Online	Download Datasheet

				NEC[NEC]
Part No.	UPD3737 UPD3737D
OCR Text	...T, output after passing through two steps of emitter follower in the application example. 5 PD3737 TIMING CHART 1 TG 1 2 R 5181 5182 5183 5184 5185 10 11 12 13 14 15 16 17 18 19 1 2 3 4 ...
Description	5150-BIT CCD LINEAR IMAGE SENSOR
File Size	189.91K / 16 Page	View it Online	Download Datasheet

				NEC[NEC]
Part No.	UPD3739 UPD3739D
OCR Text	...nd VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE. 6 PD3739 INPUT PIN CAPACITANCE (T...stage shift register clock pin capacitance CL 1L2 2L1 Reset gate clock pin capacitance C...
Description	5000 PIXELS CCD LINEAR IMAGE SENSOR
File Size	119.92K / 24 Page	View it Online	Download Datasheet

				NEC[NEC]
Part No.	UPD3747 UPD3747D
OCR Text	...nd VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE. Data Sheet S14892EJ1V0DS00 5 P...stage shift register clock pin capacitance C L 5 18 Reset gate clock pin capacitance Reset ...
Description	7400 PIXELS CCD LINEAR IMAGE SENSOR
File Size	119.97K / 20 Page	View it Online	Download Datasheet

				Fairchild Semiconductor, Corp. FAIRCHILD[Fairchild Semiconductor]
Part No.	74F161APC 74F161ASC 74F161ASJ 74F163APC 74F163ASC 74F163ASJ
OCR Text	... programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The 74F161A has an asynchronous MasterReset input that overrides all other inputs and...
Description	Synchronous Presettable Binary Counter F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
File Size	70.56K / 7 Page	View it Online	Download Datasheet

				NXP Semiconductors http:// PHILIPS[Philips Semiconductors]
Part No.	74F161A I74F161AD I74F161AN N74F161AD N74F161AN 74F163A I74F163AD I74F163AN N74F163AD N74F163AN
OCR Text	...chronous counting and loading * Two count enable inputs for n-bit cascading * Positive edge-triggered clock * Asynchronous Master Reset (74F...stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions....
Description	4-bit binary counter
File Size	111.89K / 14 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	74HC40105 74HC40105D 74HC40105DB 74HC40105N 74HC40105PW 74HCT40105 74HCT40105D 74HCT40105DB 74HCT40105N 74HCT40105PW 74HCT40105U 74HC40105U
OCR Text	... status of the FIFO is given by two status flags, data-in-ready (DIR) and data-out-ready (DOR): DIR = HIGH indicates the input stage is empty and ready to accept valid data; DIR = LOW indicates that the FIFO is full or that a previous shift...
Description	4-bit x 16-word FIFO register
File Size	199.99K / 25 Page	View it Online	Download Datasheet

For two-stage Found Datasheets File :: 17296 Search Time::1.453ms
Page :: | 1 | 2 | 3 | <4> | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |