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  divide-by-2 Datasheet PDF File

For divide-by-2 Found Datasheets File :: 6844    Search Time::1.656ms    
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    TAOS
Part No. TSL230
OCR Text ... L L H H S2 L H L H fO SCALING (divide-by) 1 2 10 100 www.taosinc.com Texas Advanced Optoelectronic Solutions Inc. 800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972) 673-0759 t t Copyright E 2001, TAOS Inc. 1 TSL230, ...
Description Programmable light-to-frequency converters, tolerance 20%
From old datasheet system

File Size 99.68K  /  8 Page

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    LT1070 LT1070CK LT1070CT LT1070HVCK LT1070HVCT LT1070HVIT LT1070HVMK LT1070IK LT1070IT LT1070MK T1070HV LT1071 LT1071CK

Linear Technology, Corp.
Linear Technology Corporation
LINER[Linear Technology]
Part No. LT1070 LT1070CK LT1070CT LT1070HVCK LT1070HVCT LT1070HVIT LT1070HVMK LT1070IK LT1070IT LT1070MK T1070HV LT1071 LT1071CK LT1071CT LT1071HV LT1071HVCK LT1071HVCT LT1071HVIT LT1071HVMK LT1071IT LT1071MK 10701FD
OCR Text ...TOPOLOGIES DELIVER MORE POWER **DIVIDE VERTICAL POWER SCALE BY 2 FOR LT1071 U U U BOOST BUCK/BOOST VO = 30V FLYBACK 1 LT1070/LT1071 ABSOLUTE MAXIMUM RATINGS Supply Voltage LT1070/LT1071 (Note 2) ........................
Description RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS 11 A SWITCHING REGULATOR, 47 kHz SWITCHING FREQ-MAX, PZFM5
RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS 抗辐射高效,5安培开关稳压器
5A and 2.5A High Efficiency Switching Regulators
From old datasheet system

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    http://
Part No. 8XC196KB
OCR Text ... 16 x 16 multiply y 3 m s 32/16 divide y 16-bit watchdog timer y 16-bit timer y 16-bit up/down counter w/capture y four 16-bit software time...by 2 instead of divide by 3 clock for a 1.5 c performance improvement faster instructions, especiall...
Description ADVANCED 16-BIT CHMOS MICROCONTROLLER ROMless OR ROM

File Size 250.30K  /  17 Page

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    SY100E446JC SY100E446JCTR SY100E446JZ SY100E446JZTR SY10E446_06 SY100E446 SY10E446 SY10E446JC SY10E446JCTR SY10E446JZ SY

MICREL[Micrel Semiconductor]
Part No. SY100E446JC SY100E446JCTR SY100E446JZ SY100E446JZTR SY10E446_06 SY100E446 SY10E446 SY10E446JC SY10E446JCTR SY10E446JZ SY10E446JZTR
OCR Text ... 1.3Gb/ s. The chips generate a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function. The conversion sequence was chosen to convert the parallel data into a serial stream from bit D0 to D3. ...
Description 4-BIT PARALLEL-TO-SERIAL CONVERTER

File Size 81.23K  /  9 Page

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    MC145073DW ON0895

Motorola, Inc
Part No. MC145073DW ON0895
OCR Text ...ng frequency is governed by the divide mode and output data rate. The divide mode can be either 1, 2, or 3. The output data rate ranges from 24 kHz to 48 kHz. The minimum clock frequency of 3.072 MHz is for a 24 kHz output rate in the clock...
Description Dual 16-Bit Stereo Audio Sigma-Delta ADC
From old datasheet system

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    MC145074D

Motorola, Inc
Part No. MC145074D
OCR Text ...sing edge of WCLK. The internal divide ratio used to generate WCLK, as well as the rising or falling edge latching of the input data can be ...by an external source. The default master mode divide rate is MODCLK/64. VSS Device Ground (Pin 8) V...
Description Stereo Audio Sigma-Delta Digital-to-Analog Converter

File Size 177.63K  /  14 Page

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    SY89533LHC SY89533LHCTR SY89533LHH SY89533LHHTR SY89532L SY89532LHC SY89532LHCTR SY89532LHH SY89532LHHTR SY89535L SY8953

MICREL[Micrel Semiconductor]
Part No. SY89533LHC SY89533LHCTR SY89533LHH SY89533LHHTR SY89532L SY89532LHC SY89532LHCTR SY89532LHH SY89532LHHTR SY89535L SY89533L SY89534L
OCR Text ...f 12 VCC-1.3V Reference M-Divide 34, 36, 38, 40, 42 44, 48, 50, 52, 54 56, 60, 70, 72 600MHz to 1000MHz (MSB) M3 13 M2 14 M1 15 ...by FSEL_A (0:2). Terminate outputs with 50 to VCC -2V. See "Output Termination Recommendations" sect...
Description 3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER

File Size 184.79K  /  15 Page

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    SY89536LHCTR SY89536LHH SY89536LHHTR SY89536L05 SY89536LHC SY89531L SY89532L SY89533L SY89534L SY89535L SY89536L

Micrel Semiconductor, Inc.
MICREL[Micrel Semiconductor]
Part No. SY89536LHCTR SY89536LHH SY89536LHHTR SY89536L05 SY89536LHC SY89531L SY89532L SY89533L SY89534L SY89535L SY89536L
OCR Text ...Default is logic HIGH. See "Pre-Divide Frequency Select" table. Analog Input/Output: Provides the reference voltage for PLL loop filter. Ana...by FSEL_A (0:2). Terminate outputs with 50 to VCC -2V. See "Output Termination Recommendations" sect...
Description 3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER 89536 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64

File Size 99.87K  /  16 Page

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    MT8940-1 MT8940AE

Mitel Semiconductor
MITEL[Mitel Networks Corporation]
Part No. MT8940-1 MT8940AE
OCR Text ...ree state output) - This is the divide by two output of C4b (pin 13) and has a falling edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). Clock 2.048 MHz (Three state output) - Thi...
Description ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL
ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL

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