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For dpll. Found Datasheets File :: 711 Search Time::2.219ms
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				Integrated Device Technology
Part No.	82V3391BEQGBLANK
OCR Text	...rnal components ? integrates t4 dpll and t0 dpll; t4 dpll locks independently or locks to t0 dpll ? supports programmable dpll bandwidth (0.5 mhz to 560 hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) ? supports 1.1x10 -5 ppm abs...
Description	SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588
File Size	56.37K / 5 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	IDT82V3012PV
OCR Text	...uit 1 f1_sel0 f1_sel1 c32o c19o dpll c2/c1.5 features ? supports at&t tr62411 and te lcordia gr-1244-core stratum 3, stratum 4 enhanced and stra tum 4 timing for ds1 interfaces ? supports itu-t g.813 option 1 clocks ? supports itu-t g.812 t...
Description	T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS SPECIALTY TELECOM CIRCUIT, PDSO56
File Size	370.84K / 30 Page	View it Online	Download Datasheet

				ZiLOG, Inc.
Part No.	Z16C3010ASG
OCR Text	... one digital phase-locked loop (dpll) for clock recovery ? 32-byte data fifos for each receiver and trans- mitter ? async mode with: C 1C8 bits/character; 1/16 to two stop bits/charac- ter in 1/16 bit increments C programmable clock factor ...
Description	2 CHANNEL(S), 10M bps, MULTI PROTOCOL CONTROLLER, PQFP100 VQFP-100
File Size	61.23K / 2 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	IDT82V3010PVG
OCR Text	...uit 1 f1_sel0 f1_sel1 c32o c19o dpll c2/c1.5 v dda v ss idt82v3010 t1/e1/oc3 telecom clock ge nerator with dual reference inputs description 2 june 19, 2006 description the idt82v3010 is a t1/e1/oc3 telecom clock generator with dual refe...
Description	T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS SPECIALTY TELECOM CIRCUIT, PDSO56
File Size	350.36K / 31 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	PCD5095 PCD5095H
OCR Text	...CED VDDA T_GMSK AGM DPLL_DATA GP_CLK7 VDD CLOCK GENERATOR (CLG) TIMING CONTROL BLOCK (TICB) VANLI PEAK-HOLD RSSI_AN SUBTRACT VBAT Vref XTAL1 XTAL2 XTAL OSCILLATOR (XOSC) WATCHDOG TIMER (WDT) CLK100 ...
Description	DECT baseband controller
File Size	78.68K / 16 Page	View it Online	Download Datasheet

				Zarlink Semiconductor
Part No.	ZL30145
OCR Text	...rial interface (spi or i 2 c) ? dpll can be configured to provide synchronous or asynchronous clock outputs ? supports ieee 1149.1 jtag boundary scan applications ? itu-t g.8262 line cards which support 1 gbe and 10 gbe interfaces ? sonet...
Description	SyncE (10 GbE) SONET/SDH Rate Conversion And Jitter Attenuator PLL
File Size	139.10K / 4 Page	View it Online	Download Datasheet

				Zarlink Semiconductor
Part No.	ZL30142
OCR Text	...m apll_clk sonet/ ethernet apll dpll ref sync /n1 /n2 i 2 c/spi jtag osco osci lock mode hold ref0 ref1 ref2 sync0 sync1 sync2 diff p_clk p_fp programmable synthesizer n*8khz zl30142 synce sonet/sdh g.8262/stratum 3 system synchronizer sh...
Description	SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer
File Size	154.70K / 4 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	MT9041B MT9041BP
OCR Text	...ns a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.04...
Description	T1/E1 System Synchronizer
File Size	72.25K / 19 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT82V3399BNLGBLANK
OCR Text	...rnal components ? integrates t0 dpll and t4 dpll; t4 dpll locks independently or locks to t0 dpll ? supports programmable dpll bandwidth (0.5 mhz to 560 hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) ? supports 1.1x10 -5 ppm abs...
Description	SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588
File Size	48.07K / 5 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	IDT82V3395BNLGBLANK
OCR Text	...ve path ? supports programmable dpll bandwidth: 18 hz, 35 hz, 70 hz and 560 hz ? provides out1~out4 output clock frequencies up to 644.53125 mhz ? includes 25mhz, 125 mhz and 156.25 mhz for cmos outputs ? includes 25.78125mhz, 128.90625 mhz...
Description	Dual Synchronous Ethernet Line Card PLL
File Size	45.29K / 5 Page	View it Online	Download Datasheet

For dpll. Found Datasheets File :: 711 Search Time::2.219ms
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