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For phased-locked Found Datasheets File :: 185 Search Time::8.313ms
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				ICST[Integrated Circuit Systems]
Part No.	MK1491-06RLF MK1491-06RLFTR MK1491-06SLF MK1491-06SLFTR MK149106 MK1491-06STR MK1491-06R MK1491-06RTR MK1491-06S
OCR Text	...ications. Using patented analog phased-locked Loop (PLL) techniques, the device accepts a 14.318 MHz crystal input to produce multiple output clocks. It provides selectable PCI local bus and AC97 audio clocks, 24 MHz and 48 MHz clocks for S...
Description	AMD GeodeClock Source AMD Geode⑩ Clock Source AMD Geode Clock Source From old datasheet system
File Size	145.92K / 10 Page	View it Online	Download Datasheet

				Linear Technology
Part No.	LTC3828EUH LTC3828EG LTC3828 3828F
OCR Text	..., 6304066, 6580258 Dual, 180 Phased Controllers Reduce Required Input Capacitance and Power Supply Induced Noise Tracking for Both Output...Locked Loop PGOOD Output VPGL IPGOOD VPG 3828f 3 LTC3828 ELECTRICAL CHARACTERISTICS ...
Description	From old datasheet system
File Size	393.09K / 32 Page	View it Online	Download Datasheet

				ZARLINK[Zarlink Semiconductor Inc]
Part No.	ZL30406QGC ZL30406QGC1 ZL30406
OCR Text	...eet The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and...
Description	SONET/SDH CLOCK MULTIPLIER PLL
File Size	296.83K / 21 Page	View it Online	Download Datasheet

				ZARLINK[Zarlink Semiconductor Inc]
Part No.	ZL30406QGG1 ZL30407 MT90401 MT9046 ZL30406 ZL30406_06 ZL30406QGC
OCR Text	...eet The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and...
Description	SONET/SDH CLOCK MULTIPLIER PLL
File Size	236.12K / 21 Page	View it Online	Download Datasheet

				ALLEGRO[Allegro MicroSystems]
Part No.	8904 A8904SLPTR-T A8904SLB-T A8904SLBTR-T A8904SLP-T
OCR Text	... *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determin...locked loop. VDD; the 5 V logic supply. Clock input for the speed reference counter. Thermal shutdow...
Description	3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
File Size	728.75K / 18 Page	View it Online	Download Datasheet

				Integrated Circuit Systems
Part No.	MK2049-34A MK2049-34SAI MK2049-34SAITR
OCR Text	Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for t...
Description	3.3 Volt Communications Clock VCXO PLL
File Size	72.53K / 8 Page	View it Online	Download Datasheet

				MTRONPTI
Part No.	K17255B K17255BA K17255BD
OCR Text	...Optic l Transmission Equipment; Phased Locked Loops (PLL's) 155.520MHz 0.5V to 4.5V Control Voltage 20ppm Stability Complementary PECL 10KH Output -40C to 85C Operating Temperature x. Ma mm 0,8 2 x. Ma mm 3,2 1 A E 255B HZ K1755.520 M E...
Description	5V Voltage Controlled Crystal Oscillators
File Size	420.39K / 2 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	SP5611SKGMPAD SP5611 SP5611KG SP5611KGMPAS SP5611SKG
OCR Text	...mmable divider is frequency and phased locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an onchip crystal controlled oscillator. The compariso...
Description	1・3GHz Bidirectional I2C Bus Controlled Synthesiser 13GHz Bidirectional I2C Bus Controlled Synthesiser
File Size	218.28K / 12 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS672M-02I ICS672M-02T ICS672-01 ICS672M-01 ICS672M-01T ICS672M-02 ICS672M-02IT
OCR Text	...ut Clock Duty Cycle, VDDIO=3.3V Phased Outputs Accuracy (Note 4) Input to Output Skew, ICLK to CLK0 (Note 5) Maximum Absolute Jitter Cycle to Cycle Jitter, 15 pF loads Notes: Conditions Referenced to GND Referenced to GND MIL-STD-883 Availa...
Description	QuadraClockQuadrature Delay Buffer QuadraClock⑩正交延迟缓冲器 QuadraClock?/a> Quadrature Delay Buffer QuadraClock Quadrature Delay Buffer QuadraClock⑩ Quadrature Delay Buffer
File Size	73.26K / 5 Page	View it Online	Download Datasheet

				ZARLINK[Zarlink Semiconductor Inc]
Part No.	ZL30415GGC ZL30415GGF ZL30415_06 MT9046 ZL30407 ZL30415 ZL30415GGF2 ZL30415GGG2
OCR Text	...ion The ZL30415 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30415 is shown in Figure 1 and a brief descr...
Description	SONET/SDH Clock Multiplier PLL
File Size	390.65K / 23 Page	View it Online	Download Datasheet

For phased-locked Found Datasheets File :: 185 Search Time::8.313ms
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