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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
EE801NDGI8
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| OCR Text |
...fective value of 4pf. reference pre-divider, reference divider, feedback-divider and post-divider each pll incorporates an 8-bit reference-...configured to support an lvds output. for lvds support, vddo1 must be set to 3.3v. vddo1 must have ... |
| Description |
VIDEO CLOCK GENERATOR, QCC24
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| File Size |
240.67K /
27 Page |
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Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
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| Part No. |
LFXP2-5E-5TN144C LFXP2-5E-5TN144I LFXP2-17E-6FN484C LFXP2-8E-5FT256C LFXP2-8E-5TN144I LFXP2-8E-5QN208I LFXP2-8E-6FTN256C LFXP2-8E-5FT256I LFXP2-8E-5FTN256C LFXP2-8E-5QN208C LFXP2-5E-5FT256C LFXP2-17E-6F484C LFXP2-8E-5FTN256I LFXP2-8E-6FT256I LFXP2-17E-7F484C LFXP2-8E-6FT256C LFXP2-8E-6FTN256I LFXP2-5E-5FTN256C LFXP2-5E-5FT256I LFXP2-5E-5FTN256I LFXP2-5E-5M132C LFXP2-30E-6FT256C LFXP2-5E-6FT256C
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| OCR Text |
...bus-lvds, mlvds, lvpecl, rsds ? pre-engineered source synchronous interfaces ? ddr / ddr2 interfaces up to 200 mhz ? 7:1 lvds interfaces su...configured in a variety of depths and widths of ram or rom. in addi- tion, latticexp2 devices contai... |
| Description |
FPGA, 311 MHz, PQFP144 20 X 20 MM, LEAD FREE, TQFP-144
FPGA, 357 MHz, PBGA484 23 X 23 MM, LEAD FREE, FPBGA-484
FPGA, 311 MHz, PBGA256 17 X 17 MM, FTBGA-256
FPGA, 311 MHz, PQFP208 28 X 28 MM, LEAD FREE, PLASTIC, QFP-208
FPGA, 357 MHz, PBGA256 17 X 17 MM, LEAD FREE, FTBGA-256
FPGA, 311 MHz, PBGA256 17 X 17 MM, LEAD FREE, FTBGA-256
FPGA, 357 MHz, PBGA484 23 X 23 MM, FPBGA-484
FPGA, 357 MHz, PBGA256 17 X 17 MM, FTBGA-256
FPGA, 420 MHz, PBGA484 23 X 23 MM, FPBGA-484
FPGA, 311 MHz, PBGA132 8 X 8 MM, CSBGA-132
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| File Size |
1,611.66K /
92 Page |
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it Online |
Download Datasheet |
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Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
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| Part No. |
LFE3-95EA-6FN672C LFE3-95EA-8FN672C LFE3-150EA-7FN672ITW LFE3-95E-7FN1156C LFE3-70E-8FN1156I LFE3-70EA-8FN484I LFE3-150EA-6FN672ITW LFE3-150EA-8FN672CTW LFE3-150EA-6FN1156C LFE3-35EA-7FTN256I
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| OCR Text |
...and up to ten plls per device ? pre-engineered source synchronous i/o ? ddr registers in i/o cells ? dedicated read/write levelling function...configured to support an array of popular data protocols including pci express, smpte, ethernet (xa... |
| Description |
FPGA, 375 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672
FPGA, 500 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672
FPGA, 420 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672
Field Programmable Gate Arrays - FPGAs 92K LUTs, 490 I/O 7 Speed FPGA, 420 MHz, PBGA1156
Field Programmable Gate Arrays - FPGAs 66.5K LUTs, 490 I/O 8 Speed FPGA, 500 MHz, PBGA1156
FPGA, 500 MHz, PBGA484 23 X 23 MM, LEAD FREE, FPBGA-484
FPGA, 375 MHz, PBGA1156
FPGA, PBGA256
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| File Size |
2,549.28K /
130 Page |
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it Online |
Download Datasheet |
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Price and Availability
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