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GSI Technology, Inc.
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Part No. |
GS88132BT-150I GS88118BGD-150I GS88118BGD-333I
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OCR Text |
...ite ?w rites all enabled bytes; active low b a , b b, b c , b d i byte write enable for dq a , dq b data i/os; active low ck i clock inp...synchronous truth table operation address us ed state diagram key e 1 e 2 e 3 adsp adsc adv w dq 3 ... |
Description |
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 256K X 32 CACHE SRAM, 7.5 ns, PQFP100 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 512K X 18 CACHE SRAM, 7.5 ns, PBGA165 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 512K X 18 CACHE SRAM, 4.5 ns, PBGA165
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File Size |
1,102.88K /
38 Page |
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GSI Technology, Inc.
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Part No. |
GS88132BT-150IV
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OCR Text |
...ite ? writes all enabled bytes; active low b a , b b, b c , b d i byte write enable for dq a , dq b data i/os; active low ck i clock inp...synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 d... |
Description |
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 256K X 32 CACHE SRAM, 7.5 ns, PQFP100
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File Size |
772.41K /
36 Page |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C4245-10AXC
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OCR Text |
...wclk signal. while wen is held active, data is continually written in to the fifo on each cycle. the output port is controlled in a similar...synchronous al most full/almost empty flag features are avail able on these devices. depth expansio... |
Description |
64/256/512/1K/2K/4K x 18 synchronous FIFOs 4K X 18 OTHER FIFO, 8 ns, PQFP64
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File Size |
499.32K /
22 Page |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C1412BV18-250BZC
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OCR Text |
...nchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiate...synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k an... |
Description |
2MX18 QDR-II BURST 2 SRAM 2M X 18 QDR SRAM, 0.45 ns, PBGA165
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File Size |
885.74K /
24 Page |
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Atmel, Corp.
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Part No. |
AT91SAM7XC128
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OCR Text |
...list signal name function type active level comments power vddin voltage regulator and adc power supply input power 3v to 3.6v vddout vo...synchronous serial controller td transmit data output rd receive data input tk transmit clock i/o rk... |
Description |
ARM Thumb-based Microcontrollers ARM公司Thumb微控制器
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File Size |
406.27K /
45 Page |
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Samsung Semiconductor Co., Ltd.
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Part No. |
M366S1623ET0
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OCR Text |
...input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm. cke clock enable masks system clock to f... |
Description |
16Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V synchronous DRAMs with SPD 16Mx64 SDRAM的内存在8Mx8BanksK的刷新,3.3社民党基于同步DRAM
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File Size |
116.25K /
12 Page |
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