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For sampled-data Found Datasheets File :: 14016 Search Time::1.953ms
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				Cypress Semiconductor
Part No.	CY7C1318CV18 CY7C1318CV18-167BZC CY7C1318CV18-167BZI CY7C1318CV18-167BZXC CY7C1318CV18-167BZXI CY7C1318CV18-200BZC CY7C1318CV18-200BZI CY7C1318CV18-200BZXC CY7C1318CV18-200BZXI CY7C1318CV18-250BZC CY7C1318CV18-250BZI CY7C1318CV18-250BZXC CY7C1318CV18-250BZXI CY7C1318CV18-267BZC CY7C1318CV18-267BZI CY7C1318CV18-267BZXC CY7C1318CV18-267BZXI
OCR Text	...nput Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the...
Description	18-Mbit DDR-II SRAM 2-Word Burst Architecture
File Size	413.44K / 29 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV25-167BZC CY7C1306AV25-167BZC CY7C1303AV25-133BZC CY7C1306AV25-133BZC
OCR Text	...Description Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1303AV25 - D[17:0] CY7C1306AV25 - D[35:0] Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserte...
Description	Memory : Sync SRAMs 18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR Architecture 18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
File Size	325.22K / 19 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1302DV25-167BZC CY7C1302DV25-167BZI CY7C1302DV25-167BZXC CY7C1302DV25-167BZXI CY7C1302DV2506 CY7C1302DV25
OCR Text	...iption InputData input signals, sampled on the rising edge of K and K clocks during valid Write operaSynchronous tions. InputWrite Port Sele...data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and no...
Description	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR垄芒 Architecture 9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture
File Size	383.22K / 18 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY2832402 CY28324PVC
OCR Text	...e input pin. When Mode input is sampled HIGH during power-on reset, this pin will be configured as 3VMREF output. When Mode input is sampled...Data Input: Data pin for serial interface. System Reset Output: Open-drain system reset output. P...
Description	FTG for Intel® Pentium® 4 CPU and Chipsets FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
File Size	182.76K / 23 Page	View it Online	Download Datasheet

				Microchip Technology, Inc. Microchip Technology Inc. MicrochipTechnology MICROCHIP[Microchip Technology]
Part No.	24C080-EP 24C080-ESN 24C080-IP 24C080-ISN 24C080-P 24C080-SN 24C160-EP 24C160-ESN 24C160-IP 24C160-ISN 24C160-P 24C160-SN 25C080 25C160 24C16 MICROCHIPTECHNOLOGYINC.-24C160-ESN 25C160T-EP 25C160T-IP 25C160T-SN 25C160T-P 25C080T-P 25C080T-IP
OCR Text	... This parameter is periodically sampled and not 100% tested. DS21147F-page 2 Preliminary (c) 1996 Microchip Technology Inc. 25C0...Data Setup Time Data Hold Time CLK Rise Time CLK Fall Time Clock High Time Clock Low Time Clock Dela...
Description	8K,16K 5.0V SPI bus EEPROM 8K/16K 5.0V SPI Bus Serial EEPROM 8K/16K 5.0V SPI总线串行EEPROM 8K/16K5.0VSPIBusSerialEEPROM 8K/16K 5.0V SPI Bus Serial EEPROM
File Size	80.69K / 12 Page	View it Online	Download Datasheet

				Catalyst Semiconductor
Part No.	CAT5129TDI-00-GT3 CAT5129TDI-00-T3 CAT5129TDI-10-GT3 CAT5129TDI-10-T3 CAT5127ZD7I-00-GT3 CAT5127ZD7I-10-GT3 CAT5127ZD7I-50-GT3 CAT5127ZI-00-GT3 CAT5129TDI-50-GT3 CAT51270708 CAT5127ZI-10-T3 CAT5127ZI-10-GT3
OCR Text	...ese parameters are periodically sampled and are not 100% tested. Doc. No. MD-2127 Rev. C 4 (c) Catalyst Semiconductor, Inc. Charact...data pins from -1V to VCC + 1V (2) IW = source or sink (3) These parameters are periodically sampled...
Description	10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 32 POSITIONS, PDSO8 32-Tap Digitally Programmable Potentiometer (DPP⑩) 32-Tap Digitally Programmable Potentiometer (DPP垄芒)
File Size	222.81K / 13 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1317AV18 CY7C1317AV18-167BZC CY7C1317AV18-200BZC CY7C1317AV18-250BZC
OCR Text	...nput/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the...
Description	18-Mbit DDR-II SRAM 4-Word Burst Architecture
File Size	359.34K / 20 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1317BV18-167BZC CY7C1317BV18-167BZI CY7C1317BV18-167BZXC CY7C1317BV18-167BZXI CY7C1317BV18-200BZC CY7C1317BV18-200BZI CY7C1317BV18-200BZXC CY7C1317BV18-200BZXI CY7C1317BV18-250BZC CY7C1317BV18-250BZI CY7C1317BV18-250BZXC CY7C1317BV18-250BZXI CY7C1317BV18-278BZC CY7C1317BV18-278BZI CY7C1317BV18-278BZXC CY7C1317BV18-278BZXI CY7C1317BV18-300BZC CY7C1317BV18-300BZI CY7C1317BV18-300BZXC CY7C1317BV18-300BZXI
OCR Text	...nput/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the...
Description	18-Mbit DDR-II SRAM 4-Word Burst Architecture
File Size	477.14K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1356C-166AXC CY7C1356C-166AXI CY7C1356C-166BGC CY7C1356C-166BGI CY7C1356C-166BGXC CY7C1356C-166BGXI CY7C1356C-166BZC CY7C1356C-166BZI CY7C1356C-166BZXC CY7C1356C-166BZXI CY7C1356C-200AXC CY7C1356C-200AXI CY7C1356C-200BGC CY7C1356C-200BGI CY7C1356C-200BGXC CY7C1356C-200BGXI CY7C1356C-200BZC CY7C1356C-200BZI CY7C1356C-200BZXC CY7C1356C-200BZXI CY7C1356C-250AXC CY7C1356C-250AXI CY7C1356C-250BGC CY7C1356C-250BGI CY7C1356C-250BGXC CY7C1356C-250BGXI CY7C1356C-250BZC CY7C1356C-250BZI CY7C1356C-250BZXC CY7C1356C-250BZXI CY7C1354C-250AXC CY7C1354C-250AXI CY7C1354C-200AXC CY7C1354C-200AXI CY7C1354C-200BGC CY7C1354C-200BGI CY7C1354C-200BGXC CY7C1354C-200BGXI CY7C1354C-200BZC CY7C1354C-200BZI CY7C1354C-200BZXC CY7C1354C-200BZXI
OCR Text	...t one of the address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct wr...data pins. OE is masked during the data portion of a Write sequence, during the first clock when eme...
Description	9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
File Size	515.72K / 28 Page	View it Online	Download Datasheet

				Alliance Semiconductor ...
Part No.	AS4C32M16SM AS4C32M16SM-7TIN
OCR Text	...put data is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high - z state (two - clock latency)...data input/output: data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51 are nc for x8; and ...
Description	PC133-compliant
File Size	2,741.77K / 73 Page	View it Online	Download Datasheet

For sampled-data Found Datasheets File :: 14016 Search Time::1.953ms
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