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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1297H-133AXC
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| OCR Text |
...deasse rted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging ...linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. thi... |
| Description |
1-Mbit (64K x 18) Flow-Through Sync SRAM; Architecture: Standard Sync, Flow-through; Density: 1 Mb; Organization: 64Kb x 18; Vcc (V): 3.1 to 3.6 V
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| File Size |
490.56K /
15 Page |
 View
it Online |
Download Datasheet
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1339G-166BGC CY7C1339G-133AXE CY7C1339G-200BGXI CY7C1339G-200BGXC CY7C1339G-250BGXC
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| OCR Text |
...n deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging ...linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? proces... |
| Description |
4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 3.5 ns, PBGA119
4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 4 ns, PQFP100
4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 2.8 ns, PBGA119
4-Mbit (128K x 32) Pipelined Sync SRAM 128K X 32 CACHE SRAM, 2.6 ns, PBGA119
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| File Size |
382.78K /
18 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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