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				ICST[Integrated Circuit Systems]
Part No.	ICS9248-72 ICS9248YF-72
OCR Text	...d spectrum enable 0= Running 1= tristate all outputs PCICLK 33.325 34.505 35.725 36.99 38.12 39.245 40.505 30.00 33.405 35 37.83 40.00 32.125 33.33 28.33 33.40 IOAPIC 16.66 17.25 17.86 18.49 19.06 19.62 20.25 15.00 16.70 17.50 18.91 20.00 1...
Description	Frequency Timing Generator for PENTIUM II Systems
File Size	519.05K / 12 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc.
Part No.	ICS9248-73 ICS9248YF-73-T ICS9248YF-73LF-T AV9248F-73
OCR Text	...spectrum enable 0 - Running 1 - tristate all outputs Notes: 1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000. * These output frequencies are not synchronous to CPUCLK and do not ...
Description	Frequency timing generator for Pentium II system Frequency Timing Generator for Pentium II Systems 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48
File Size	355.22K / 15 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc. ADDtek, Corp.
Part No.	ICS9248-77 ICS9248YF-77 ICS9248YF-77LF AV9248F-77
OCR Text	...nabled ea 0 - Running Bit 0 1 - tristate all outputs Note 1 0 0 0 Note 1: Default at power-up will be for latched logic inputs to define frequency. * These output frequencies are not synchronous to CPUCLK and do not have Spread Spe...
Description	Frequency timing generator for Pentium II system 820 Single Chip Clock, Supports 66.6 - 150MHz Frequency Timing Generator for PENTIUM II Systems 20-Bit Buffers/Drivers With 3-State Outputs 56-SSOP -40 to 85 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 SSOP-48 Replaced by SN74ABT16373A : 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85 频率的奔腾II系统时序发生
File Size	311.66K / 14 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-78 ICS9248YF-78
OCR Text	...spectrum enable 0 - Running 1 - tristate all outputs Notes: 1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000. * These output frequencies are not synchronous to CPUCLK and do not ...
Description	810 Single Chip Clock, Supports 66.6 - 150MHz Frequency Timing Generator for Pentium II Systems
File Size	573.87K / 13 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc.
Part No.	ICS9248-81 ICS9248YF-81 AV9248F-81
OCR Text	...nabled ea 0 - Running Bit 0 1 - tristate all outputs Note 1: Default at power-up will be for latched logic inputs to define frequency. Note 2: PWD = Power-Up Default XXXX Note 1 0 1 0 6 ICS9248-81 Byte 1: CPU, Active/Inactive ...
Description	Frequency generator and integrated buffer Single Chip, SIS 530/620 133MHz System Clock with AGP Clocks Frequency Generator & Integrated Buffers 133.3 MHz, OTHER CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48
File Size	541.76K / 18 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. ICST[Integrated Circuit Systems] Integrated Circuit Syst...
Part No.	ICS9248-87 ICS9248YF-87 ICS9248YF-87LF AV9248F-87
OCR Text	...5% Center Spread 0 - Running 1- tristate all outputs Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 1) All entries selectable through I2C. Entries 1 -16 are also selectable through...
Description	Frequency generator and integrated buffer for Celeron and PII/III 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48 16-Bit Transparent D-Type Latches With 3-State Outputs 48-TSSOP -40 to 85 810E Single Chip Clock, Supports 66 - 155MHz (P) Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ Frequency Generator & Integrated Buffers for Celeron & PII/III?
File Size	359.72K / 13 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... ICST[Integrated Circuit Systems] Integrated Device Technology, Inc.
Part No.	ICS9248-90 ICS9248YF-90-T ICS9248YF-90LF-T
OCR Text	...d spectrum enable 0- Running 1- tristate all outputs Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 4 ICS9248-90 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = dis...
Description	BX Single Clock, Supports 66.6 - 150MHz Frequency Generator & Integrated Buffers for PENTIUM/ProTM 132.99 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48
File Size	280.34K / 16 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-92 ICS9248YG-92
OCR Text	...Select Functions Functionality tristate Testmode CPU HI - Z TCLK/2 1 PCI, PCI_F HI - Z TCLK/4 1 SDRAM HI - Z TCLK/2 1 REF HI - Z TCLK 1 24 MHz Selection HI - Z TCLK/4 1 48 MHz Selection HI - Z TCLK/21 Notes: 1. TCLK ...
Description	Single Chip; BX/MX/MX , System Clock Mobile Pentium IITM System Clock Chip
File Size	339.46K / 14 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. ICST[Integrated Circuit Systems]
Part No.	ICS9248-97 ICS9248YF-97-T ICS9248YF-97LF-T
OCR Text	...pectrum enabled 0 - Running 1 - tristate all outputs 0 0 0 Note 1: Default at power-up will be for latched logic inputs to define frequency. 4 ICS9248-97 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit ...
Description	180 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85 Frequency Generator & Integrated Buffers Frequency Timing Generator for PENTIUM II Systems
File Size	463.92K / 14 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-98 ICS9248YF-98-T AV9248F-98-T
OCR Text	...5% Center Spread 0 - Running 1- tristate all outputs PWD 0,0101 Note1 0 1 0 Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. Third party brands and names are the property...
Description	Frequency generator and integrated buffer for Celeron and PII/III Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85 Frequency Generator & Integrated Buffers for Celeron & PII/III??/span>
File Size	504.81K / 15 Page	View it Online	Download Datasheet

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