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1g 2g Datasheet PDF File

For 1g 2g Found Datasheets File :: 1334 Search Time::1.031ms
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				HITACHI[Hitachi Semiconductor]
Part No.	HD74BC240A
OCR Text	...and has two active low enables (1g and 2g). Each enable independently controls 4 buffers. Features * * * * Input/Output are at high impedance state when power supply is off. Built in input pull up circuit can make input pins be open, wh...
Description	Octal Buffers/Line Drivers With 3 State Outputs
File Size	38.66K / 8 Page	View it Online	Download Datasheet

				HITACHI[Hitachi Semiconductor]
Part No.	HD74BC244A
OCR Text	...and has two active low enables (1g and 2g). Each enable independently controls 4 buffers. Features * * * * Input/Output are at high impedance state when power supply is off. Built in input pull up circuit can make input pins be open, wh...
Description	Octal Buffers/Line Drivers with 3-state outputs Octal Buffers/Line Drivers With 3 State Outputs
File Size	37.82K / 8 Page	View it Online	Download Datasheet

				MICRO-LINEAR[Micro Linear Corporation]
Part No.	ML65244 ML65244CK ML65244CS ML65L244CS ML65L244CK
OCR Text	...Is Obsolete VCC 20 VCC 2g 19 1g 1 YAO 18 BO 17 YA1 16 B1 15 YA2 14 B2 13 YA3 12 B3 11 10 GND 2 AO 3 YBO 4 A1 5 YB1 6 A2 7 YB2 8 A3 9 YB3 1 ML65244/ML65L244 PIN CONFIGURATION 20-P...
Description	2.5V 144-mc CPLD - NOT RECOMMENDED for NEW DESIGN High Speed Dual Quad Buffer/Line Drivers
File Size	117.41K / 8 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	PCK2509SA PCK2509SADH
OCR Text	...led separately via the control (1g and 2g) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing P...
Description	50-150 MHz 1:9 SDRAM clock driver
File Size	73.10K / 10 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	PCK2509SL PCK2509SLDH
OCR Text	...led separately via the control (1g and 2g) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing P...
Description	50-150 MHz 1:9 SDRAM clock driver
File Size	73.69K / 10 Page	View it Online	Download Datasheet

For 1g 2g Found Datasheets File :: 1334 Search Time::1.031ms
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