| |
|
 |
Integrated Device Techn...
|
| Part No. |
89HPES16T4AG2
|
| OCR Text |
...on options ? automatic per port link width negotiation to x8, x4, x2 or x1 ? automatic lane reversal on all ports ? automatic polarity inver...transaction layer data link layer multiplexer / demultiplexer transaction layer data link layer mult... |
| Description |
Low latency cut-through switch architecture
|
| File Size |
273.47K /
32 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES16NT16G2
|
| OCR Text |
...r x1 ports ? automatic per port link width negotiation (x8 ? x4 ? x2 ? x1) ? crosslink support ? automatic lane reversal ? per lane s...transaction layer data link layer serdes phy logical layer multiplexer / demultiplexer transaction l... |
| Description |
Supports 128 Bytes to 2 KB maximum payload size
|
| File Size |
244.50K /
33 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES16H16
|
| OCR Text |
...supports powerdown modes at the link level (l0, l0s, l1, l2/l3 ready and l3) and at the device level (d0, d3 hot ) ? unused serdes disabled ...transaction layers. the pes16h16 can operate either as a store and forward switch or a cut-through s... |
| Description |
Low-latency cut-through switch architecture
|
| File Size |
232.46K /
36 Page |
View
it Online |
Download Datasheet |
| |
|
|
Macronix 旺宏
|
| Part No. |
MX98715A 98715A
|
| OCR Text |
...ows a single RJ-45 connector to link with the other IEEE802.3uP/N:PM0537
compliant device without re-configuration. In MX98715A, an innov...transaction, these four bits provide the bus command. During the data phase, these four bits provide... |
| Description |
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
From old datasheet system
|
| File Size |
222.94K /
32 Page |
View
it Online |
Download Datasheet |
| |
|
|
Macronix 旺宏
|
| Part No. |
MX98715 98715
|
| OCR Text |
...ows a single RJ-45 connector to link with the other IEEE802.3u-compliant device without re-configuration. In MX98715, an innovative and prop...transaction, these four bits provide the bus command. During the data phase, these four bits provide... |
| Description |
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
From old datasheet system
|
| File Size |
156.75K /
28 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES12NT12G2
|
| OCR Text |
...t x1 ports ? automatic per port link width negotiation (x4 ? x2 ? x1) ? crosslink support ? automatic lane reversal ? per lane serdes co...transaction layer data link layer x1 (ports 0 through 3) serdes phy logical layer multiplexer / demu... |
| Description |
Low latency cut-through architecture
|
| File Size |
243.85K /
32 Page |
View
it Online |
Download Datasheet |
| |
|
|
MCNIX[Macronix International]
|
| Part No. |
MX98L715BEC
|
| OCR Text |
... including 3 wake up events : - link Change (link-on) - Wake Up Frames - Magic Packet * 100/10 Base-T NWAY auto-negotiation function * Suppo...transaction, these four bits provide the bus command. During the data phase, these four bits provide... |
| Description |
3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER
|
| File Size |
573.04K /
50 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Technology, Inc.
|
| Part No. |
89HPES32H8ZAALI 89HPES32H8ZAARI
|
| OCR Text |
...n priority ? automatic per port link width negotiation to x8, x4, x2 or x1 ? automatic lane reversal on all ports ? automatic polarity inver...transaction layer serdes x8/x4/x2/x1 dl/transaction layer serdes x8/x4/x2/x1 dl/transaction layer se... |
| Description |
32-Lane 8-Port PCI Express System Interconnect Switch PCI BUS CONTROLLER, PBGA900
|
| File Size |
392.37K /
40 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES12N3
|
| OCR Text |
...s ? supports automatic per port link with negotiation (x4, x2, or x1) ? supports static lane reversal on all ports ? supports polarity inver...transaction layer data link layer route table port arbitration scheduler serdes phy logical layer se... |
| Description |
Supports one virtual channel
|
| File Size |
271.25K /
28 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES4T4G2
|
| OCR Text |
... / demux transaction layer data link layer (port 0) (port 1) serdes phy logical layer mux / demux transaction layer data link layer serdes phy logical layer mux / demux transaction layer data link layer (port 2) (port 3) serdes phy logical ... |
| Description |
Support for Max Payload Size up to 2Kbytes
|
| File Size |
420.92K /
30 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
