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  tri-linear Datasheet PDF File

For tri-linear Found Datasheets File :: 1373    Search Time::1.329ms    
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    TGA4823-2-SM TGA4823-2-SM-15

TriQuint Semiconductor
Part No. TGA4823-2-SM TGA4823-2-SM-15
OCR Text ...triquint semiconductor: www. tri quint.com (972)994- 8465 fax (972)994-8504 info-mmw@tqs.com table ii recommended linear operating conditions table i absolute maximum ratings 1/ symbol parameter value notes vd-vg drain to gate volta...
Description 9.9 -12.5 Gb/s Linear/Limiting Optical Modulator Driver
9.9 to 12.5 Gb/s Linear/Limiting Optical Modulator Driver

File Size 1,714.05K  /  16 Page

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    Z380

ZiLOG, Inc.
Part No. Z380
OCR Text ...ress Bus (outputs, active High, tri-state). These non-multiplexed address signals provide a linear memory address space of four gigabytes. The 32-address signals are also used to access I/O devices. /BACK Bus Acknowledge (output, active Low...
Description MICROPROCESSOR(高性能微处理器)

File Size 583.53K  /  115 Page

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    Cypress Semiconductor Corp.
Part No. CY7C1353G-117AXC
OCR Text ... easy bank selection and output tri-state control. in order to avoid bus contention, the output driver s are synchronously tri-stated during...linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd...
Description 4-Mbit (256K x 18) Flow-through SRAM with NoBLArchitecture 4兆位56 × 18)流通过总线延迟⑩建筑的SRAM

File Size 217.30K  /  13 Page

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    82596DX 82596SX A82596SX

INTEL[Intel Corporation]
Part No. 82596DX 82596SX A82596SX
OCR Text ...ata Bus lines are bidirectional tri-state lines that provide the general purpose data path between the 82596 and memory With the 82596DX the...Linear Mode The 82596 has a 32-bit memory address range Any memory structure can reside anywhere wi...
Description HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

File Size 750.52K  /  77 Page

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    82596CA

INTEL[Intel Corporation]
Part No. 82596CA
OCR Text ...ata Bus lines are bidirectional tri-state lines that provide the general purpose data path between the 82596 and memory With the 82596 the b...Linear Mode The 82596 has a 32-bit memory address range Any memory structure can reside anywhere wi...
Description HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR

File Size 725.26K  /  76 Page

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    Zilog
Microprocessor
Part No. Z-380
OCR Text ...ress Bus (outputs, active High, tri-state). These non-multiplexed address signals provide a linear memory address space of four gigabytes. The 32-address signals are also used to access I/O devices. /BACK Bus Acknowledge (output, active Low...
Description Microprocessor

File Size 670.85K  /  115 Page

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    CY7C1339G CY7C1339G-250BGXI CY7C1339G-133AXC CY7C1339G-133AXI CY7C1339G-133BGC CY7C1339G-133BGI CY7C1339G-133BGXC CY7C13

CYPRESS[Cypress Semiconductor]
Part No. CY7C1339G CY7C1339G-250BGXI CY7C1339G-133AXC CY7C1339G-133AXI CY7C1339G-133BGC CY7C1339G-133BGI CY7C1339G-133BGXC CY7C1339G-133BGXI CY7C1339G-166AXC CY7C1339G-166AXI CY7C1339G-166BGC CY7C1339G-166BGI CY7C1339G-166BGXC CY7C1339G-166BGXI CY7C1339G-200AXC CY7C1339G-200AXI CY7C1339G-200BGC CY7C1339G-200BGI CY7C1339G-200BGXC CY7C1339G-200BGXI CY7C1339G-250AXC CY7C1339G-250AXI CY7C1339G-250BGC CY7C1339G-250BGI CY7C1339G-250BGXC CY7C1339G-100AXC
OCR Text ...n deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging fr...linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is...
Description 4-Mbit (128K x 32) Pipelined Sync SRAM
4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

File Size 334.92K  /  17 Page

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    Z8038018FSC Z8L38010FSC Z380

ZILOG[Zilog, Inc.]
Part No. Z8038018FSC Z8L38010FSC Z380
OCR Text ...ress Bus (outputs, active High, tri-state). These non-multiplexed address signals provide a linear memory address space of four gigabytes. The 32-address signals are also used to access I/O devices. /BACK Bus Acknowledge (output, active Low...
Description MICROPROCESSOR

File Size 631.78K  /  115 Page

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    Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
Part No. CY7C1345G CY7C1345G-133BGXI CY7C1345G-100AXC CY7C1345G-100AXI CY7C1345G-100BGC CY7C1345G-100BGI CY7C1345G-100BGXC CY7C1345G-100BGXI CY7C1345G-117AXC CY7C1345G-117AXI CY7C1345G-117BGC CY7C1345G-117BGI CY7C1345G-117BGXC CY7C1345G-117BGXI CY7C1345G-133AXC CY7C1345G-133AXI CY7C1345G-133BGC CY7C1345G-133BGI CY7C1345G-133BGXC
OCR Text ...n deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging fr...linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is...
Description 4-Mbit (128K x 36) Flow-Through Sync SRAM 128K X 36 CACHE SRAM, 6.5 ns, PBGA119
4-Mbit (128K x 36) Flow-Through Sync SRAM 128K X 36 CACHE SRAM, 8 ns, PQFP100

File Size 328.03K  /  17 Page

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For tri-linear Found Datasheets File :: 1373    Search Time::1.329ms    
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