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Altera Corporation
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| Part No. |
EP910I EP1810 EP910 EP610 EP610I EP910LC-30
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| OCR Text |
...ock configuration also supports gated clock structures.
748
Altera Corporation
Classic EPLD Family Data Sheet
Figure 2. Classic...delay prediction, and detailed timing analysis for systemlevel performance evaluation.
Timing Mod... |
| Description |
CPLD, EP910 Family, ECMOS Process, 450 Gates, 24 Macro Cells, 24 Reg., 24 User I/Os, 5V Supply, 30 Speed Grade, 44LDCC
The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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| File Size |
293.93K /
42 Page |
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IDT
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| Part No. |
IDT5T2010 5T2010_DATASHEET
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| OCR Text |
...selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE...delay, or invert on each bank (See Control Summary table) Function select inputs for divide-by-2, di... |
| Description |
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK?
From old datasheet system
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| File Size |
154.86K /
23 Page |
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it Online |
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Price and Availability
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