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SGS Thomson Microelectronics
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| Part No. |
AN1152
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| OCR Text |
...ase represents the ideal way to manage the emulated eeprom to get the maximum number of cycles/byte. it is reported purely as an example, since it is really an untypical flow for eeprom data management. it consists of the following operativ... |
| Description |
ST9 - OPTIMIZING THE USAGE OF THE ST92F120 EEPROM
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| File Size |
172.43K /
16 Page |
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意法半导
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| Part No. |
L6725TR
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| OCR Text |
...f 20a. the device is capable to manage minimum on-times (t on ) shorter than 100ns making possible conversions with very low duty cycle and very high switching frequency. in order to guarantee a real overcurrent protection, also with very... |
| Description |
Low cost adjustable step-down controller
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| File Size |
482.20K /
27 Page |
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it Online |
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SGS Thomson Microelectronics
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| Part No. |
AN1187
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| OCR Text |
...memories by allowing the engine manage- ment software to be upgraded along with a service. economy and performance enhancements can be made even after the car has been sold. other embedded products, such as digital cameras and gps receivers... |
| Description |
ALL YOU NEED TO KNOW BEFORE CHOOSING A FLASH MEMORY
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| File Size |
118.98K /
16 Page |
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it Online |
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TOSHIBA
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| Part No. |
JTC83230-0011S
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| OCR Text |
........ , if the mode is manage of addition or substruction operation, operation is the same as that for or key. and when gt mode is specified, the result of addition/subtruction is added to the gt memory. if the mode is ma... |
| Description |
Single-Chip CMOS LSI for Calculators with Printers (applicable printer heads: M-31 manufactured by EPSON)
Single-Chip CMOS LSI for Calculators with Printers
(applicable printer heads: M-31 manufactured by EPSON)
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| File Size |
432.82K /
25 Page |
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it Online |
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ST Microelectronics
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| Part No. |
CLIENT STPCD0166BTI3 STPCD0175BTI3 STPCD0175BTC3
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| OCR Text |
...ion interface able to directly manage up to 3 pci masters at a time. ? translation of pci cycles to isa bus. ? translation of isa master initiated cycle to pci. ? support for burst read/write from pci master. ? the pci clock runs at a ... |
| Description |
STPC CLIENT DATASHEET / PC COMPATIBLE EMBEDED MICROPROCESSOR
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| File Size |
1,009.64K /
61 Page |
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it Online |
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ST Microelectronics
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| Part No. |
L6717
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| OCR Text |
... adjustable lsless startup to manage pre-biased output vfqfpn48 package applications hybrid high-current vrm / vrd for desktop / server / workstation / ipc cpus supporting pvi and svi interface high-density dc / dc converters descri... |
| Description |
High-efficiency hybrid AM2r2 controller
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| File Size |
1,094.50K /
56 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CYD04S18V18-250BBXC CYD18S18V18-200BBXC CYD18S18V18-167BBXC
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| OCR Text |
...deterministic access control to manage address collisions ? deterministic flag output upon collision detection ? collision detection on back-to-back clock cycles ? first busy address readback ? advanced features for improved high-speed dat... |
| Description |
256K X 18 DUAL-PORT SRAM, 7.2 ns, PBGA256 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FBGA-256
1M X 18 DUAL-PORT SRAM, 9 ns, PBGA256 19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256
1M X 18 DUAL-PORT SRAM, 11 ns, PBGA256 19 X 19 MM, 1.70 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256
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| File Size |
791.37K /
51 Page |
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it Online |
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Bourns, Inc.
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| Part No. |
PPC403GB-KA28C-1
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| OCR Text |
...vidu- ally, allowing the biu to manage devices or memory banks with differing control, timing, or bus width requirements. risc execution unit cache unit instruction cache unit data 2-channel dma controller port jtag dram controller i/o co... |
| Description |
32-Bit Microprocessor 32位微处理
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| File Size |
364.34K /
44 Page |
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it Online |
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