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Zarlink Semiconductor, Inc.
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| Part No. |
ZL38010DCF ZL38010DCE1 ZL38010DCF1
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| OCR Text |
... pcm i/o control decode vdd vss pwrdn ic ms1 ms2 a/ format ms5 ms4 ms3 ms6 linear sel timing adpcmi adpcmo enb1 enb2/f0od bclk f0i mclk c2o en1 en2 pcmo1 pcmi1 pcmo2 pcmi2 full duplex quad transcoder
zl38010 data sheet 2 zarlink semicond... |
| Description |
Low Power Quad ADPCM Transcoder A/MU-LAW, ADPCM CODEC, PDSO28
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| File Size |
480.87K /
27 Page |
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Zarlink
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| Part No. |
MT9315
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| OCR Text |
...
Linear
Rin
VDD
VSS
pwrdn
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram
1
MT9315
Advance Information
MD2 ENA2 MD1 ENA1 IC IC BCLK/C4i Rin Sin VSS MCLK IC IC IC
Figu... |
| Description |
CMOS Acoustic Echo Canceller
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| File Size |
206.27K /
29 Page |
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it Online |
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ST Microelectronics
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| Part No. |
STA508
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| OCR Text |
...pf 15 m3 in1a in1a ibias config pwrdn pwrdn fault tri-state th_war th_war +3.3v in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in2a in1b in2a in2b protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m... |
| Description |
40V 4.5A QUAD POWER HALF BRIDGE
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| File Size |
145.01K /
9 Page |
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it Online |
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ST Microelectronics
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| Part No. |
STA50813TR
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| OCR Text |
...30pf 15 m3 in1a in1a v l config pwrdn pwrdn fault tri-state th_war th_war +3.3v in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in2a in1b in2a in2b protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m... |
| Description |
40V 4.5A QUAD POWER HALF BRIDGE
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| File Size |
513.15K /
10 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
MT9125
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| OCR Text |
...
Transcoder 2
VDD
VSS
pwrdn
IC
MS1 MS2
A/ FORMAT
MS3 MS4
Figure 1 - Functional Block Diagram
8-73
MT9125
Preliminary Information
24 PIN PDIP
MCLK F0i C2o DSTo DSTi BCLK VSS ENB2 ENB1 MS1 MS2 MS3
1 2 ... |
| Description |
CMOS Dual ADPCM Transcoder
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| File Size |
190.50K /
17 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CYS25G0101DX-AEXC CYS25G0101DX-10
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| OCR Text |
... fifo_err txclko fifo_rst reset pwrdn logic block diagram [+] feedback
cys25g0101dx document number: 38-02009 rev. *m page 3 of 18 clocking the source clock for the transmit data path is selectable from either the recovered clock or an... |
| Description |
SONET OC-48 Transceiver; Features: SONET/SDH OC-48/STM-16; Bellcore and ITU Jitter Compliance; Standard: SONET/OC-48; TRANSCEIVER, PQFP120
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| File Size |
465.34K /
18 Page |
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it Online |
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Price and Availability
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