| PART |
Description |
Maker |
| CY7C1429AV18 CY7C1422AV18 |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture(2字Burst结构36-Mbit DDR-II SIO SRAM) 36兆位的DDR - II二氧化硅的SRAM 2字突发架构（2字突发结36 -兆位的DDR - II二氧化硅的SRAM
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture(2字Burst结构6-Mbit DDR-II SIO SRAM) 36兆位的DDR - II二氧化硅的SRAM 2字突发架构（2字突发结36 -兆位的DDR - II二氧化硅的SRAM
|
Cypress Semiconductor Corp.
|
| CY7C1423KV18 CY7C1429KV18 |
36-Mbit DDR II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1529AV18 CY7C1529AV18-167BZC CY7C1522AV18 CY7C |
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1423BV18 CY7C1423BV18-167BZC CY7C1422BV18 CY7C |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| CY7C1168V18-400BZXC CY7C1168V18-375BZXC CY7C1168V1 |
1M X 18 DDR SRAM, 0.45 ns, PBGA165 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 1M X 18 DDR SRAM, 0.45 ns, PBGA165
2M X 8 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1518JV18-250BZC CY7C1518JV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1277V18-300BZC CY7C1266V18-300BZXC CY7C1266V18 |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 9 DDR SRAM, 0.45 ns, PBGA165
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 8 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1548V18-300BZC CY7C1548V18-300BZI CY7C1548V18- |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 8M X 8 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
