| PART |
Description |
Maker |
| ADN2819ACPZ-CML-RL1 ADN2819ACP-CML ADN2819 EVAL-AD |
Multi Rate Limiting Amplifier and Clock and Data Recovery ICs
Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
N/A
|
AD[Analog Devices]
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| CO-2500E8.192MHZ OC-2500DAT10.000MHZ OC-2500CAT16. |
OCXO, SINE OUTPUT, 8.192 MHz
OCXO, CLOCK, 10 MHz, HCMOS/ACMOS OUTPUT
OCXO, CLOCK, 16.384 MHz, CMOS/TTL OUTPUT
OCXO, CLOCK, 10 MHz, HCMOS OUTPUT
OCXO, CLOCK, 8.192 MHz, HCMOS/ACMOS OUTPUT
OCXO, CLOCK, 10 MHz, CMOS/TTL OUTPUT
|
Vectron International, Inc.
|
| CS19208CBI |
OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device OC-192/48/12/3仓库/前向纠错/ PM和异步映射器装置
|
Applied Micro Circuits, Corp.
|
| IDT72V73250DA IDT72V73250 IDT72V73250BB |
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
|
IDT[Integrated Device Technology]
|
| SH713609 SH7137 |
SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer
|
Renesas Electronics Corporation
|
| W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
| S19205 |
STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock
|
Applied Micro Circuits Corp.
|
| NBSG53A NBSG53AMN NBSG53AMNR2 NBSG53ABAR2 NBSG53AB |
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
|
ONSEMI[ON Semiconductor]
|
| MAX3991 MAX3991UTG |
DC to 4-GBPS Dual 1:2 MUX/Repeater/Equalizer 48-VQFN -40 to 85
10Gbps Clock and Data Recovery with Limiting Amplifier
10 Gbps clock and data recovery with limiting amplifier
|
Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
|
