| PART |
Description |
Maker |
| MT49H16M18C MT49H32M9C MT49H16M18CFM-XX MT49H32M9C |
288Mb SIO REDUCED LATENCY(RLDRAM II)
|
Micron Technology, Inc.
|
| SI6821DQ |
P-Ch, Reduced Qg, Fast Switching MOSFET Schottky Diode
From old datasheet system
P-Channel Reduced Qg / MOSFET with Schottky Diode
P-Channel, Reduced Qg, MOSFET with Schottky Diode P沟道，减Qg和与MOSFET的肖特基二极
|
Vishay Siliconix
Vishay Intertechnology, Inc.
|
| MT49H8M36 |
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
|
Micron Technology
|
| SI4850EY SI4850EY-E3 SI4850EY-T1 SI4850EY-T1-E3 |
N-Channel Reduced Qg, Fast-Switching MOSFET N沟道Qg，快速开关MOSFET
N-Channel Reduced Qg, Fast Switching MOSFET N沟道减少Qg和，快速开关MOSFET
N-Channel Reduced Qg/ Fast Switching MOSFET
|
Vishay Intertechnology, Inc.
Vishay Siliconix
|
| LTC2415-1 LTC2415 LTC2415IGN LTC2415CGN LTC2415-1C |
24-Bit No Latency ADCs with Differential Input and Differential Reference
24-Bit No Latency Delta Sigma ADC with Differential Input and Differential Reference
24-Bit No Latency Delta Sigma ADC with Differential Input, 50/60Hz Rejection
|
LINER[Linear Technology]
|
| CY7C1165V18 CY7C1163V18 CY7C1161V18 CY7C1176V18 CY |
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 9 QDR SRAM, 0.45 ns, PBGA165
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18兆位的国防评估报告⑩- II SRAM字突发架构（2.5周期读写延迟
18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| LTC2413 LTC2413CGN LTC2413IGN |
24-Bit No Latency Delta Sigma with Simultaneous 50Hz/60Hz Rejection ADC,
24-Bit No Latency ADC, with Simultaneous 50Hz/60Hz Rejection
|
Linear Technology
|
| LTC2412 LTC2424 LTC2412CGN |
2-Channel Differential Input 24-Bit No Latency Delta Sigma ADC
2-Ch Differential Input 24-Bit No Latency Delta Sigma
16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-SSOP -40 to 85
16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
|
Linear Technology Corporation
Linear Technology, Corp.
|
| LTC2401 LTC2401CMS LTC2401IMS LTC2402 LTC2402CMS L |
1-/2-Channel 24-Bit µPower No Latency Delta-Sigma ADC in MSOP-10; Package: MSOP; No of Pins: 10; Temperature Range: -40°C to 85°C 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10
1-/2-Channel 24-Bit µPower No Latency Delta-Sigma ADC in MSOP-10; Package: MSOP; No of Pins: 10; Temperature Range: 0°C to 70°C 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10
1-/2-Channel 24-Bit µPower No Latency Delta-Sigma ADC in MSOP-10; Package: MSOP; No of Pins: 10; Temperature Range: -40°C to 85°C 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10
1-/2-Channel 24-Bit mPower No Latency DSTMADCs in MSOP-10
1-/2-Channel 24-Bit PowerNo Latency Delta-SigmaADC in MSOP-10
1-/2-Channel 24-Bit µPowerNo Latency Delta-Sigma™ADC in MSOP-10
|
Linear Technology, Corp.
|
| T81L0003A-BK T81L0003A T81L0003A-AD T81L0003A-AK T |
Reduced I/O 8-bit MCU
|
TMT[Taiwan Memory Technology]
|
| LTC2495 |
No Latency ADC
|
Linear Integrated Systems
|
| CY7C1261V18 CY7C1261V18-300BZC CY7C1261V18-300BZI |
36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor
|
