| PART |
Description |
Maker |
| 74ALS74A 74ALS74AD 74ALS74ADB 74ALS74AN 74ALS74 |
Dual D-type flip-flop with set and reset ALS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
PHILIPS[Philips Semiconductors]
NXP Semiconductors N.V.
|
| 5962F9863201VCC 5962F9863201V9A 5962F9863201VXC AC |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Radiation Hardened Dual J-K Flip-Flop with Set and Reset 辐射硬化的设置和复位JK触发
|
Intersil Corporation
Intersil, Corp.
|
| SN74LS377D SN74LS377N SN74LS379D SN74LS379DW SN74L |
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
OCTAL D FLIP-FLOP WITH ENABLE HEX D FLIP-FLOP WITH ENABLE 4-BIT D FLIP-FLOP WITH ENABLE
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| 74LV109 74LV109D 74LV109DB 74LV109N 74LV109PW 74LV |
Dual JK flip-flop with set and reset; positive-edge trigger LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV |
CLP SINE LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| MC74HC109 ON1335 |
Dual J-K Flip-Flop with Set and Rest
From old datasheet system
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
Motorola, Inc
ON Semi
|
| ACTS74HMSR-02 |
Dual D Type Flip Flop with Set and Reset, Advanced Logic, CMOS; Temperature Range: -55°C to 125°C; Package: Die (Military Visual) ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
|
Intersil, Corp.
|
| 74ALS109AN 74ALS109A 74ALS109AD |
Dual J-K positive edge-triggered flip-flop with set and reset ALS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
|
Rochester Electronics, LLC
PHILIPS[Philips Semiconductors]
NXP Semiconductors
|
| 74F11200 74F112SJ 74F112 74F112PC 74F112SC 74F112S |
From old datasheet system
Dual JK Negative Edge-Triggered Flip-Flop; Package: SOP; No of Pins: 16; Container: Tape & Reel F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| MC100ELT23 MC100EL12DTR2 MC10H131FNR2 MC100H640FNR |
5V Dual Differential PECL to TTL Translator
5V ECL Low Impedance Driver
Dual Type D Master-Slave Flip-Flop
ECL/TTL Clock Driver
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5V ECL ÷4 Divider
Quad 2-Input NOR Gate
3.3V ECL Dual Differential Data and Clock D-Type Flip-Flop with Set and Reset
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V / 5V Triple ECL Input to LVPECL/PECL Output Translator
|
ON Semiconductor
|
| MC10H135 MC10H135FN MC10H135L MC10H135P ON0754 MC1 |
From old datasheet system
L SUFFIX CERAMIC PACKAGE
Dual J-K Master-Slave Flip-Flop
Dual In/Single Out Autoswitching Power MUX, Manual/Auto Sw, Adj. Cur Limit, Adj. Vol Threshold 8-TSSOP -40 to 85
Autoswitching Power Mux 8-TSSOP -40 to 85 10H SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC20
|
ONSEMI[ON Semiconductor]
Motorola, Inc.
Motorola Mobility Holdings, Inc.
|
