| PART |
Description |
Maker |
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| CY2PP3220AI CY2PP3220AIT CY2PP3220 |
Dual 1:10 Differential Clock/Data Fanout Buffer
Dual 1:10 Differential Clock / Data Fanout Buffer 2PP SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
|
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor, Corp.
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| MAX9320A MAX9320 MAX9320EUAT |
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
1:2 Differential LVPECL/ LVECL/HSTL Clock and Data Drivers
|
Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
|
| SY87701V SY87701VHC SY87701VZC |
5V/3.3V 32-1250Mbps AnyRateCLOCK AND DATA RECOVERY
5V/3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY
5V/3.3V 32-1250Mbps AnyRate⑩ CLOCK AND DATA RECOVERY
|
Micrel Semiconductor,Inc.
MICREL[Micrel Semiconductor]
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
| SY87721L |
3.3V 28Mbps-2.7Gbps AnyRateTM Clock and Data Recovery with Integrated Clock Multiplier Unit
|
Micrel Semiconductor
|
| NBSG53AMNG NBSG53AMNR2G NBSG53A_06 NBSG53ABA NBSG5 |
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS
|
ONSEMI[ON Semiconductor]
|
| SY54023ARMG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY100EL15LZG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY100EL17VZG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
