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CY7C1250V18-300BZI - 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的DDR - II SRAM2字突发架构（2.0周期读写延迟 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 1M X 36 DDR SRAM, 0.45 ns, PBGA165

CY7C1250V18-300BZI_2582596.PDF Datasheet
 
Part No. CY7C1250V18-300BZI CY7C1246V18-333BZI CY7C1246V18-300BZI CY7C1248V18-333BZI CY7C1250V18-333BZI CY7C1257V18-300BZI CY7C1248V18-375BZI CY7C1250V18-375BZI CY7C1246V18-375BZI CY7C1257V18-333BZI CY7C1248V18-300BZI CY7C1246V18-333BZC CY7C1246V18-300BZXI CY7C1248V18-375BZXI CY7C1246V18-300BZC CY7C1248V18-375BZXC CY7C1248V18-333BZXI CY7C1248V18-333BZXC CY7C1248V18-300BZXI CY7C1248V18-300BZXC CY7C1246V18-375BZXC CY7C1246V18-375BZXI CY7C1246V18-333BZXC CY7C1246V18-333BZXI CY7C1246V18-300BZXC CY7C1248V18-375BZC CY7C1248V18-333BZC CY7C1248V18-300BZC CY7C1246V18-375BZC CY7C1257V18-300BZC CY7C1257V18-300BZXC
Description 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的DDR - II SRAM2字突发架构（2.0周期读写延迟
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 1M X 36 DDR SRAM, 0.45 ns, PBGA165
File Size 1,030.62K  /  27 Page  

Maker
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.

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 Full text search : 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的DDR - II SRAM2字突发架构（2.0周期读写延迟 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 1M X 36 DDR SRAM, 0.45 ns, PBGA165

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