| PART |
Description |
Maker |
| CY7C1529AV18-200BZXI CY7C1529AV18-250BZXI |
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 8M X 9 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1523AV18-200BZI CY7C1523AV18-300BZI CY7C1524AV |
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 2M X 36 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 4M X 18 DDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1523V18-200BZCES CY7C1523V18-250BZCES CY7C1523 |
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress
|
| CY7C1992BV18 CY7C1992BV18-167BZC CY7C1992BV18-167B |
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1424AV18 CY7C1424AV18-167BZC CY7C1424AV18-300B |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1316BV18 CY7C1318BV18 CY7C1916BV18 CY7C1320BV1 |
18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst结构,18-Mbit DDR-II SRAM) 18兆位的DDR - II SRAM字突发架构（2字突发结18 -兆位的DDR - II SRAM的）
18-Mbit DDR-II SRAM 2-Word Burst Architecture(2瀛?urst缁??,18-Mbit DDR-II SRAM)
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| K7J163682B K7J161882B |
512Kx36 & 1Mx18 DDR II SIO b2 SRAM
|
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
|
| CY7C1550KV18-450BZC CY7C1550KV18-400BZC CY7C1548KV |
Sync SRAM; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress Semiconductor, Corp.
|
| CY7C1250V18-300BZI CY7C1246V18-333BZI CY7C1246V18- |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的DDR - II SRAM2字突发架构（2.0周期读写延迟
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 1M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1568KV18-550BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
